commit ca8c6f90cba089f33252408fb2602b43e6fd4c90
Author: luck <luck@vector4d.cn>
Date:   Tue Jan 30 09:41:56 2024 +0800

    init code

diff --git a/ft2004-devboard-d4-dsk_std.dts b/ft2004-devboard-d4-dsk_std.dts
new file mode 100644
index 0000000..f7e8743
--- /dev/null
+++ b/ft2004-devboard-d4-dsk_std.dts
@@ -0,0 +1,556 @@
+# 1 "ft2004-devboard-d4-dsk.dts"
+# 1 "<built-in>"
+# 1 "<command-line>"
+# 1 "ft2004-devboard-d4-dsk.dts"
+
+
+
+
+
+
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+# 1 "ft2004-generic-psci-soc.dtsi" 1
+
+
+
+
+
+
+
+# 1 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 1
+# 9 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h"
+# 1 "../u-boot/include/dt-bindings/interrupt-controller/irq.h" 1
+# 10 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 2
+# 9 "ft2004-generic-psci-soc.dtsi" 2
+
+/ {
+ compatible = "phytium,ft2004";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+  ethernet0 = &gmac0;
+  ethernet1 = &gmac1;
+ };
+
+ psci {
+  compatible = "arm,psci-1.0";
+  method = "smc";
+  cpu_suspend = <0xc4000001>;
+  cpu_off = <0x84000002>;
+  cpu_on = <0xc4000003>;
+  sys_poweroff = <0x84000008>;
+  sys_reset = <0x84000009>;
+ };
+
+ cpus {
+  #address-cells = <0x2>;
+  #size-cells = <0x0>;
+
+  cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   numa-node-id = <0>;
+   clocks = <&scpi_dvfs 0>;
+  };
+
+  cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,armv8";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   numa-node-id = <0>;
+   clocks = <&scpi_dvfs 0>;
+  };
+
+  cpu2: cpu@100 {
+   device_type = "cpu";
+   compatible = "arm,armv8";
+   reg = <0x0 0x100>;
+   enable-method = "psci";
+   numa-node-id = <0>;
+   clocks = <&scpi_dvfs 1>;
+  };
+
+  cpu3: cpu@101 {
+   device_type = "cpu";
+   compatible = "arm,armv8";
+   reg = <0x0 0x101>;
+   enable-method = "psci";
+   numa-node-id = <0>;
+   clocks = <&scpi_dvfs 1>;
+  };
+ };
+
+ gic: interrupt-controller@29900000 {
+  compatible = "arm,gic-v3";
+  #interrupt-cells = <3>;
+  #address-cells = <2>;
+  #size-cells = <2>;
+  ranges;
+  interrupt-controller;
+  reg = <0x0 0x29900000 0 0x20000>,
+        <0x0 0x29980000 0 0x80000>,
+        <0x0 0x29c00000 0 0x10000>,
+        <0x0 0x29c10000 0 0x10000>,
+        <0x0 0x29c20000 0 0x10000>;
+  interrupts = <1 9 4>;
+
+  its: gic-its@29920000 {
+   compatible = "arm,gic-v3-its";
+   msi-controller;
+   reg = <0x0 0x29920000 0x0 0x20000>;
+  };
+ };
+
+ timer {
+  compatible = "arm,armv8-timer";
+  interrupts = <1 13 8>,
+        <1 14 8>,
+        <1 11 8>,
+        <1 10 8>;
+  clock-frequency = <48000000>;
+ };
+
+ pmu {
+  compatible = "arm,armv8-pmuv3";
+  interrupts = <1 7 8>;
+ };
+
+ clocks {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  ranges;
+
+  clk250mhz: clk250mhz {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <250000000>;
+  };
+
+  sysclk_48mhz: clk48mhz {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <48000000>;
+  };
+
+  sysclk_600mhz: clk600mhz {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <600000000>;
+  };
+ };
+
+ soc {
+  compatible = "simple-bus";
+  #address-cells = <2>;
+  #size-cells = <2>;
+  dma-coherent;
+  ranges;
+
+  gpio0: gpio@28004000 {
+   compatible = "phytium,gpio";
+   reg = <0x0 0x28004000 0x0 0x1000>;
+   interrupts = <0 10 4>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   porta {
+    compatible = "phytium,gpio-port";
+    reg = <0>;
+    nr-gpios = <8>;
+   };
+
+   portb {
+    compatible = "phytium,gpio-port";
+    reg = <1>;
+    nr-gpios = <8>;
+   };
+  };
+
+  gpio1: gpio@28005000 {
+   compatible = "phytium,gpio";
+   reg = <0x0 0x28005000 0x0 0x1000>;
+   interrupts = <0 11 4>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   porta {
+    compatible = "phytium,gpio-port";
+    reg = <0>;
+    nr-gpios = <8>;
+   };
+
+   portb {
+    compatible = "phytium,gpio-port";
+    reg = <1>;
+    nr-gpios = <8>;
+   };
+  };
+
+  uart0: uart@28000000 {
+   compatible = "arm,pl011", "arm,primecell";
+   reg = <0x0 0x28000000 0x0 0x1000>;
+   baud = <115200>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   interrupts = <0 6 4>;
+   clocks = <&sysclk_48mhz &sysclk_48mhz>;
+   clock-names = "uartclk", "apb_pclk";
+  };
+
+  uart1: uart@28001000 {
+   compatible = "arm,pl011", "arm,primecell";
+   reg = <0x0 0x28001000 0x0 0x1000>;
+   baud = <115200>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   interrupts = <0 7 4>;
+   clocks = <&sysclk_48mhz &sysclk_48mhz>;
+   clock-names = "uartclk", "apb_pclk";
+  };
+
+  uart2: uart@28002000 {
+   compatible = "arm,pl011", "arm,primecell";
+   reg = <0x0 0x28002000 0x0 0x1000>;
+   baud = <115200>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   interrupts = <0 8 4>;
+   clocks = <&sysclk_48mhz &sysclk_48mhz>;
+   clock-names = "uartclk", "apb_pclk";
+  };
+
+  uart3: uart@28003000 {
+   compatible = "arm,pl011", "arm,primecell";
+   reg = <0x0 0x28003000 0x0 0x1000>;
+   baud = <115200>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   interrupts = <0 9 4>;
+   clocks = <&sysclk_48mhz &sysclk_48mhz>;
+   clock-names = "uartclk", "apb_pclk";
+  };
+
+  sdci: sdci@28207c00 {
+   compatible = "phytium,sdci";
+   reg = <0x0 0x28207c00 0x0 0x100>;
+   interrupts = <0 20 4>,
+         <0 21 4>,
+         <0 22 4>;
+   clocks = <&sysclk_600mhz &sysclk_600mhz>;
+   clock-names = "phytium_sdc_clk";
+   no-sdio;
+   no-mmc;
+   no-dma-coherent;
+  };
+
+  watchdog0: watchdog@2800a000 {
+   compatible = "arm,sbsa-gwdt";
+   reg = <0x0 0x2800b000 0x0 0x1000>,
+         <0x0 0x2800a000 0x0 0x1000>;
+   interrupts = <0 16 4>;
+   timeout-sec = <30>;
+  };
+
+  watchdog1: watchdog@28016000 {
+   compatible = "arm,sbsa-gwdt";
+   reg = <0x0 0x28017000 0x0 0x1000>,
+         <0x0 0x28016000 0x0 0x1000>;
+   interrupts = <0 17 4>;
+   timeout-sec = <30>;
+  };
+
+  rtc0: rtc@2800d000 {
+   compatible = "phytium,rtc";
+   reg = <0x0 0x2800d000 0x0 0x1000>;
+   clocks = <&sysclk_48mhz>;
+   clock-names = "rtc_pclk";
+   interrupts = <0 4 4>;
+   status = "disabled";
+  };
+
+  i2c0: i2c@28006000 {
+   compatible = "snps,designware-i2c";
+   reg = <0x0 0x28006000 0x0 0x1000>;
+   interrupts = <0 12 4>;
+   clocks = <&sysclk_48mhz>;
+   status = "disabled";
+  };
+
+  i2c1: i2c@28007000 {
+   compatible = "snps,designware-i2c";
+   reg = <0x0 0x28007000 0x0 0x1000>;
+   interrupts = <0 13 4>;
+   clocks = <&sysclk_48mhz>;
+   status = "disabled";
+  };
+
+  i2c2: i2c@28008000 {
+   compatible = "snps,designware-i2c";
+   reg = <0x0 0x28008000 0x0 0x1000>;
+   interrupts = <0 14 4>;
+   clocks = <&sysclk_48mhz>;
+   status = "disabled";
+  };
+
+  i2c3: i2c@28009000 {
+   compatible = "snps,designware-i2c";
+   reg = <0x0 0x28009000 0x0 0x1000>;
+   interrupts = <0 15 4>;
+   clocks = <&sysclk_48mhz>;
+   status = "disabled";
+  };
+
+  spi0: spi@2800c000 {
+   compatible = "phytium,spi";
+   interrupts = <0 18 4>;
+   reg = <0x0 0x2800c000 0x0 0x1000>;
+   clocks = <&sysclk_48mhz>;
+   num-cs = <4>;
+  };
+
+  spi1: spi@28013000 {
+   compatible = "phytium,spi";
+   interrupts = <0 19 4>;
+   reg = <0x0 0x28013000 0x0 0x1000>;
+   clocks = <&sysclk_48mhz>;
+   num-cs = <4>;
+  };
+
+  qspi: qspi@28014000 {
+   compatible = "phytium,qspi";
+   reg = <0x0 0x28014000 0x0 0x1000>,
+         <0x0 0x0 0x0 0x02000000>;
+   reg-names = "qspi", "qspi_mm";
+   clocks = <&sysclk_600mhz>;
+
+   flash@0 {
+    spi-rx-bus-width = <1>;
+    spi-max-frequency = <600000000>;
+   };
+  };
+
+  pcie: pcie {
+   compatible = "pci-host-ecam-generic";
+   device_type = "pci";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x40000000 0x0 0x10000000>;
+   msi-parent = <&its>;
+   bus-range = <0x0 0xff>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0 28 4>,
+     <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0 29 4>,
+     <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0 30 4>,
+     <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0 31 4>;
+   ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00f00000>,
+     <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
+     <0x03000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
+  };
+
+  phytium_axi_setup: stmmac-axi-config {
+   snps,wr_osr_lmt = <0>;
+   snps,rd_osr_lmt = <0>;
+   snps,blen = <0 0 0 0 16 8 4>;
+  };
+
+  gmac0: eth@2820c000 {
+   compatible = "snps,dwmac";
+   reg = <0x0 0x2820c000 0x0 0x2000>;
+   interrupts = <0 49 4>;
+   interrupt-names = "macirq";
+   clocks = <&clk250mhz>;
+   clock-names = "stmmaceth";
+   status = "disabled";
+
+   snps,pbl = <16>;
+   snps,fixed-burst;
+   snps,axi-config = <&phytium_axi_setup>;
+   snps,force_sf_dma_mode;
+   snps,multicast-filter-bins = <64>;
+   snps,perfect-filter-entries = <128>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <4096>;
+   max-frame-size = <9000>;
+  };
+
+  gmac1: eth@28210000 {
+   compatible = "snps,dwmac";
+   reg = <0x0 0x28210000 0x0 0x2000>;
+   interrupts = <0 50 4>;
+   interrupt-names = "macirq";
+   clocks = <&clk250mhz>;
+   clock-names = "stmmaceth";
+   status = "disabled";
+
+   snps,pbl = <16>;
+   snps,fixed-burst;
+   snps,axi-config = <&phytium_axi_setup>;
+   snps,force_sf_dma_mode;
+   snps,multicast-filter-bins = <64>;
+   snps,perfect-filter-entries = <128>;
+   snps,rx-queues-to-use = <2>;
+   tx-fifo-depth = <4096>;
+   rx-fifo-depth = <4096>;
+   max-frame-size = <9000>;
+  };
+
+  can0: can@28207000 {
+   compatible = "phytium,can";
+   reg = <0x0 0x28207000 0x0 0x400>;
+   interrupts = <0 87 4>;
+   clocks = <&sysclk_600mhz>;
+   clock-names = "phytium_can_clk";
+   tx-fifo-depth = <0x40>;
+   rx-fifo-depth = <0x40>;
+  };
+
+  can1: can@28207400 {
+   compatible = "phytium,can";
+   reg = <0x0 0x28207400 0x0 0x400>;
+   interrupts = <0 91 4>;
+   clocks = <&sysclk_600mhz>;
+   clock-names = "phytium_can_clk";
+   tx-fifo-depth = <0x40>;
+   rx-fifo-depth = <0x40>;
+  };
+
+  can2: can@028207800 {
+   compatible = "phytium,can";
+   reg = <0x0 0x28207800 0x0 0x400>;
+   interrupts = <0 92 4>;
+   clocks = <&sysclk_600mhz>;
+   clock-names = "phytium_can_clk";
+   tx-fifo-depth = <0x40>;
+   rx-fifo-depth = <0x40>;
+  };
+
+  hda: hda@28206000 {
+   compatible = "phytium,hda";
+   reg = <0 0x28206000 0x0 0x1000>;
+   interrupts = <0 23 4>;
+   clocks = <&sysclk_48mhz>;
+   clock-names = "phytium_hda_clk";
+  };
+
+  mbox: mailbox@2a000000 {
+   compatible = "phytium,mbox";
+   reg = <0x0 0x2a000000 0x0 0x1000>;
+   interrupts = <0 48 4>;
+   #mbox-cells = <1>;
+   clocks = <&sysclk_48mhz>;
+   clock-names = "apb_pclk";
+  };
+
+  sram: sram@2a006000 {
+   compatible = "phytium,ft2004-sram-ns","mmio-sram";
+   reg = <0x0 0x2a006000 0x0 0x2000>;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x0 0x0 0x2a006000 0x2000>;
+
+   scpi_lpri: scpi-shmem@0 {
+    compatible = "phytium,ft2004-scpi-shmem";
+    reg = <0x1000 0x800>;
+   };
+  };
+
+  scpi_protocol: scpi {
+   compatible = "arm,scpi";
+   mboxes = <&mbox 0>;
+   shmem = <&scpi_lpri>;
+
+   clocks {
+    compatible = "arm,scpi-clocks";
+
+    scpi_dvfs: scpi_clocks@0 {
+     compatible = "arm,scpi-dvfs-clocks";
+     #clock-cells = <1>;
+     clock-indices = <0>, <1>;
+     clock-output-names = "c0", "c1";
+    };
+   };
+
+   scpi_sensors: sensors {
+    compatible = "arm,scpi-sensors";
+    #thermal-sensor-cells = <1>;
+   };
+  };
+ };
+};
+# 12 "ft2004-devboard-d4-dsk.dts" 2
+
+/{
+ model = "FT-2000/4-D4-DSK Development Board";
+ compatible = "phytium,ft-2004";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+  stdout-path = "uart1:115200n8";
+ };
+
+ memory@00{
+  device_type = "memory";
+  reg = <0x0 0x80000000 0x1 0x00000000>;
+ };
+
+ memory@01{
+  device_type = "memory";
+  reg = <0x20 0x00000000 0x1 0x00000000>;
+ };
+
+ firmware {
+  optee {
+   compatible = "linaro,optee-tz";
+   method = "smc";
+  };
+ };
+};
+
+&rtc0 {
+ status = "ok";
+};
+
+&uart1 {
+ status = "ok";
+};
+
+&gmac0 {
+ status = "ok";
+ phy-mode = "rgmii-rxid";
+};
+
+&gmac1 {
+ status = "disabled";
+ phy-mode = "rgmii-rxid";
+};
+
+&spi0 {
+ status = "ok";
+};
+
+&qspi {
+ status = "ok";
+};
+
+&i2c0 {
+ status = "ok";
+};
+
+&i2c1 {
+ status = "ok";
+};