forked from luck/tmp_suning_uos_patched
200 lines
4.1 KiB
C
200 lines
4.1 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
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* Copyright (C) 2001 MIPS Technologies, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <asm/branch.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/inst.h>
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#include <asm/ptrace.h>
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#include <asm/uaccess.h>
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/*
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* Compute the return address and do emulate branch simulation, if required.
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*/
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int __compute_return_epc(struct pt_regs *regs)
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{
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unsigned int *addr, bit, fcr31;
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long epc;
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union mips_instruction insn;
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epc = regs->cp0_epc;
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if (epc & 3)
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goto unaligned;
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/*
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* Read the instruction
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*/
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addr = (unsigned int *) epc;
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if (__get_user(insn.word, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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regs->regs[0] = 0;
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switch (insn.i_format.opcode) {
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/*
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* jr and jalr are in r_format format.
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*/
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case spec_op:
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switch (insn.r_format.func) {
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case jalr_op:
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regs->regs[insn.r_format.rd] = epc + 8;
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/* Fall through */
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case jr_op:
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regs->cp0_epc = regs->regs[insn.r_format.rs];
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break;
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}
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break;
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/*
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* This group contains:
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* bltz_op, bgez_op, bltzl_op, bgezl_op,
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* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
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*/
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case bcond_op:
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switch (insn.i_format.rt) {
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case bltz_op:
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case bltzl_op:
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if ((long)regs->regs[insn.i_format.rs] < 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgez_op:
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case bgezl_op:
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if ((long)regs->regs[insn.i_format.rs] >= 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bltzal_op:
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case bltzall_op:
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regs->regs[31] = epc + 8;
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if ((long)regs->regs[insn.i_format.rs] < 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgezal_op:
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case bgezall_op:
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regs->regs[31] = epc + 8;
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if ((long)regs->regs[insn.i_format.rs] >= 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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}
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break;
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/*
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* These are unconditional and in j_format.
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*/
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case jal_op:
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regs->regs[31] = regs->cp0_epc + 8;
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case j_op:
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epc += 4;
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epc >>= 28;
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epc <<= 28;
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epc |= (insn.j_format.target << 2);
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regs->cp0_epc = epc;
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break;
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/*
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* These are conditional and in i_format.
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*/
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case beq_op:
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case beql_op:
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if (regs->regs[insn.i_format.rs] ==
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regs->regs[insn.i_format.rt])
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bne_op:
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case bnel_op:
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if (regs->regs[insn.i_format.rs] !=
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regs->regs[insn.i_format.rt])
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case blez_op: /* not really i_format */
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case blezl_op:
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/* rt field assumed to be zero */
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if ((long)regs->regs[insn.i_format.rs] <= 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case bgtz_op:
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case bgtzl_op:
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/* rt field assumed to be zero */
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if ((long)regs->regs[insn.i_format.rs] > 0)
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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/*
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* And now the FPA/cp1 branch instructions.
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*/
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case cop1_op:
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if (!cpu_has_fpu)
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fcr31 = current->thread.fpu.soft.fcr31;
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else
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asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
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bit = (insn.i_format.rt >> 2);
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bit += (bit != 0);
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bit += 23;
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switch (insn.i_format.rt) {
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case 0: /* bc1f */
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case 2: /* bc1fl */
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if (~fcr31 & (1 << bit))
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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case 1: /* bc1t */
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case 3: /* bc1tl */
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if (fcr31 & (1 << bit))
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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else
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epc += 8;
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regs->cp0_epc = epc;
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break;
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}
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break;
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}
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return 0;
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unaligned:
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printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
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force_sig(SIGBUS, current);
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return -EFAULT;
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}
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