forked from luck/tmp_suning_uos_patched
161 lines
4.1 KiB
C
161 lines
4.1 KiB
C
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/*
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* linux/arch/m32r/kernel/setup_mappi.c
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*
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* Setup routines for Renesas MAPPI Board
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*
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* Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto
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*/
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#include <linux/config.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
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#ifndef CONFIG_SMP
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typedef struct {
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unsigned long icucr; /* ICU Control Register */
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} icu_data_t;
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#endif /* CONFIG_SMP */
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icu_data_t icu_data[NR_IRQS];
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static void disable_mappi_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
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outl(data, port);
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}
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static void enable_mappi_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
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outl(data, port);
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}
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static void mask_and_ack_mappi(unsigned int irq)
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{
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disable_mappi_irq(irq);
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}
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static void end_mappi_irq(unsigned int irq)
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{
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enable_mappi_irq(irq);
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}
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static unsigned int startup_mappi_irq(unsigned int irq)
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{
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enable_mappi_irq(irq);
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return (0);
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}
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static void shutdown_mappi_irq(unsigned int irq)
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{
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unsigned long port;
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port = irq2port(irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct hw_interrupt_type mappi_irq_type =
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{
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"MAPPI-IRQ",
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startup_mappi_irq,
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shutdown_mappi_irq,
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enable_mappi_irq,
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disable_mappi_irq,
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mask_and_ack_mappi,
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end_mappi_irq
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};
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void __init init_IRQ(void)
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{
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static int once = 0;
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if (once)
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return;
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else
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once++;
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#ifdef CONFIG_NE2000
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/* INT0 : LAN controller (RTL8019AS) */
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irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_INT0].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_INT0].action = 0;
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irq_desc[M32R_IRQ_INT0].depth = 1;
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icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
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disable_mappi_irq(M32R_IRQ_INT0);
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#endif /* CONFIG_M32R_NE2000 */
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/* MFT2 : system timer */
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irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_MFT2].action = 0;
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irq_desc[M32R_IRQ_MFT2].depth = 1;
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_mappi_irq(M32R_IRQ_MFT2);
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#ifdef CONFIG_SERIAL_M32R_SIO
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/* SIO0_R : uart receive data */
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irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO0_R].action = 0;
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irq_desc[M32R_IRQ_SIO0_R].depth = 1;
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icu_data[M32R_IRQ_SIO0_R].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO0_R);
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/* SIO0_S : uart send data */
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irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO0_S].action = 0;
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irq_desc[M32R_IRQ_SIO0_S].depth = 1;
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icu_data[M32R_IRQ_SIO0_S].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO0_S);
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/* SIO1_R : uart receive data */
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irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO1_R].action = 0;
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irq_desc[M32R_IRQ_SIO1_R].depth = 1;
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icu_data[M32R_IRQ_SIO1_R].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO1_R);
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/* SIO1_S : uart send data */
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irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO1_S].action = 0;
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irq_desc[M32R_IRQ_SIO1_S].depth = 1;
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icu_data[M32R_IRQ_SIO1_S].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO1_S);
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#endif /* CONFIG_SERIAL_M32R_SIO */
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#if defined(CONFIG_M32R_PCC)
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/* INT1 : pccard0 interrupt */
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irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_INT1].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_INT1].action = 0;
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irq_desc[M32R_IRQ_INT1].depth = 1;
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icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
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disable_mappi_irq(M32R_IRQ_INT1);
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/* INT2 : pccard1 interrupt */
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irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_INT2].handler = &mappi_irq_type;
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irq_desc[M32R_IRQ_INT2].action = 0;
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irq_desc[M32R_IRQ_INT2].depth = 1;
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icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
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disable_mappi_irq(M32R_IRQ_INT2);
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#endif /* CONFIG_M32RPCC */
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}
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