AcoSail/kernel_optimize_test
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kernel_optimize_test/include/asm-arm/arch-pxa/pxa3xx_nand.h

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[MTD] [NAND] support for pxa3xx This is preliminary since: 1. It supports only _one_ chip select at the moment. As there is no existing platforms available using two chip selects of the NAND controller, it shall really not include code for supporting the 2nd chip select for now, as such code cannot be verified. 2. It resorts to the default and simpliest memory based badblock table 3. Only limited types of nand flash are currently supported. Most PXA3xx processors come with on-chip NAND flash dies, so there isn't much flexibility for other types of NAND. 4. The NAND controller should be configured to detect the device's ID, thus making it difficult to use nand_scan_ident() to assist the detection process (though it's not impossible) TODO: fix all the above limitations of cuz :-) Signed-off-by: eric miao <eric.miao@marvell.com> Cc: Sergey Podstavin <spodstavin@ru.mvista.com> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2008-02-14 15:48:23 +08:00
#ifndef __ASM_ARCH_PXA3XX_NAND_H
#define __ASM_ARCH_PXA3XX_NAND_H
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
struct pxa3xx_nand_platform_data {
/* the data flash bus is shared between the Static Memory
* Controller and the Data Flash Controller, the arbiter
* controls the ownership of the bus
*/
int enable_arbiter;
struct mtd_partition *parts;
unsigned int nr_parts;
};
[ARM] pxa: add pxa3xx NAND device and clock sources A pxa3xx_set_nand_info() is also introduced to set the PXA3xx NAND driver specific platform_data structure pointer. Signed-off-by: Eric Miao <eric.miao@marvell.com> Cc: Sergey Podstavin <spodstavin@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-02 15:22:03 +08:00
extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
[MTD] [NAND] support for pxa3xx This is preliminary since: 1. It supports only _one_ chip select at the moment. As there is no existing platforms available using two chip selects of the NAND controller, it shall really not include code for supporting the 2nd chip select for now, as such code cannot be verified. 2. It resorts to the default and simpliest memory based badblock table 3. Only limited types of nand flash are currently supported. Most PXA3xx processors come with on-chip NAND flash dies, so there isn't much flexibility for other types of NAND. 4. The NAND controller should be configured to detect the device's ID, thus making it difficult to use nand_scan_ident() to assist the detection process (though it's not impossible) TODO: fix all the above limitations of cuz :-) Signed-off-by: eric miao <eric.miao@marvell.com> Cc: Sergey Podstavin <spodstavin@ru.mvista.com> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2008-02-14 15:48:23 +08:00
#endif /* __ASM_ARCH_PXA3XX_NAND_H */
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