forked from luck/tmp_suning_uos_patched
102 lines
2.3 KiB
YAML
102 lines
2.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel ComboPhy Subsystem
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maintainers:
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- Dilip Kota <eswara.kota@linux.intel.com>
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description: |
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Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
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controllers. A single Combophy provides two PHY instances.
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properties:
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$nodename:
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pattern: "combophy(@.*|-[0-9a-f])*$"
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compatible:
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items:
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- const: intel,combophy-lgm
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- const: intel,combo-phy
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clocks:
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maxItems: 1
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reg:
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items:
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- description: ComboPhy core registers
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- description: PCIe app core control registers
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reg-names:
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items:
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- const: core
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- const: app
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resets:
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maxItems: 4
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reset-names:
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items:
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- const: phy
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- const: core
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- const: iphy0
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- const: iphy1
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intel,syscfg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: Chip configuration registers handle and ComboPhy instance id
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intel,hsio:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: HSIO registers handle and ComboPhy instance id on NOC
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intel,aggregation:
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type: boolean
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description: |
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Specify the flag to configure ComboPHY in dual lane mode.
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intel,phy-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Mode of the two phys in ComboPhy.
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See dt-bindings/phy/phy.h for values.
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"#phy-cells":
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const: 1
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required:
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- compatible
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- clocks
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- reg
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- reg-names
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- intel,syscfg
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- intel,hsio
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- intel,phy-mode
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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combophy@d0a00000 {
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compatible = "intel,combophy-lgm", "intel,combo-phy";
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clocks = <&cgu0 1>;
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#phy-cells = <1>;
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reg = <0xd0a00000 0x40000>,
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<0xd0a40000 0x1000>;
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reg-names = "core", "app";
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resets = <&rcu0 0x50 6>,
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<&rcu0 0x50 17>,
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<&rcu0 0x50 23>,
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<&rcu0 0x50 24>;
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reset-names = "phy", "core", "iphy0", "iphy1";
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intel,syscfg = <&sysconf 0>;
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intel,hsio = <&hsiol 0>;
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intel,phy-mode = <PHY_TYPE_PCIE>;
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intel,aggregation;
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};
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