License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2012-06-05 23:23:08 +08:00
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/****************************************************************************/
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/*
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* m525xsim.h -- ColdFire 525x System Integration Module support.
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*
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* (C) Copyright 2012, Steven king <sfking@fdwdc.com>
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* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m525xsim_h
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#define m525xsim_h
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/****************************************************************************/
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2012-09-19 11:52:12 +08:00
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/*
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* This header supports ColdFire 5249, 5251 and 5253. There are a few
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* little differences between them, but most of the peripheral support
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* can be used by all of them.
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*/
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2012-06-05 23:23:08 +08:00
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#define CPU_NAME "COLDFIRE(m525x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* The 525x has a second MBAR region, define its address.
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*/
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#define MCF_MBAR2 0x80000000
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/*
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* Define the 525x SIM register set addresses.
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*/
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2012-07-15 19:55:01 +08:00
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
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2012-07-15 20:01:08 +08:00
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#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
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#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
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2012-09-14 14:09:59 +08:00
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#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
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2012-07-15 19:42:47 +08:00
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#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
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#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
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2012-08-17 14:48:16 +08:00
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#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
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#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
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#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
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#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
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#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
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#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
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#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
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#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
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#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
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#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
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#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
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#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
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2012-06-05 23:23:08 +08:00
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2012-09-14 13:36:02 +08:00
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#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
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#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
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#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
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#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
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#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
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#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
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#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
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#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
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#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
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#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
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#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
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#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
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#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
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#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
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2012-06-05 23:23:08 +08:00
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#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
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#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
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#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
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2012-09-19 11:52:12 +08:00
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#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
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#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
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2012-06-05 23:23:08 +08:00
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/*
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* Secondary Interrupt Controller (in MBAR2)
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*/
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#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
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#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
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#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
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#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
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#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
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#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
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#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
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#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
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#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
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#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
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((((i) - MCFINTC2_VECBASE) / 8) * 4))
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#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
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/*
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* Timer module.
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*/
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
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#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
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/*
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* QSPI module.
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*/
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2014-05-15 01:06:46 +08:00
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#define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */
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2012-06-05 23:23:08 +08:00
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#define MCFQSPI_SIZE 0x40 /* Register set size */
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2012-09-19 11:52:12 +08:00
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#ifdef CONFIG_M5249
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#define MCFQSPI_CS0 29
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#define MCFQSPI_CS1 24
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#define MCFQSPI_CS2 21
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#define MCFQSPI_CS3 22
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#else
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2012-06-05 23:23:08 +08:00
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#define MCFQSPI_CS0 15
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#define MCFQSPI_CS1 16
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#define MCFQSPI_CS2 24
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#define MCFQSPI_CS3 28
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2012-09-19 11:52:12 +08:00
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#endif
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2012-06-05 23:23:08 +08:00
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/*
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* I2C module.
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*/
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2016-05-21 19:57:20 +08:00
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#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */
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2012-06-05 23:23:08 +08:00
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#define MCFI2C_SIZE0 0x20 /* Register set size */
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2016-05-21 19:57:20 +08:00
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#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base address I2C1 */
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2012-06-05 23:23:08 +08:00
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#define MCFI2C_SIZE1 0x20 /* Register set size */
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2012-09-19 11:52:12 +08:00
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2012-06-05 23:23:08 +08:00
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/*
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* DMA unit base addresses.
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*/
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#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
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#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
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#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
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#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
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/*
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* Some symbol defines for the above...
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*/
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#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
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#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
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#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
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#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
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#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
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#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
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#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
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#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
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#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
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#define MCF_IRQ_I2C0 29
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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#define MCF_IRQ_UART0 73 /* UART0 */
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#define MCF_IRQ_UART1 74 /* UART1 */
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/*
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* Define the base interrupt for the second interrupt controller.
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* We set it to 128, out of the way of the base interrupts, and plenty
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* of room for its 64 interrupts.
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*/
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#define MCFINTC2_VECBASE 128
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#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
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#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
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#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
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#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
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#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
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#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
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#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
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2012-09-19 11:52:12 +08:00
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#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
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2012-06-05 23:23:08 +08:00
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#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
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#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
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/*
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* General purpose IO registers (in MBAR2).
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*/
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#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
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#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
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#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
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#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
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#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
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#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
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#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
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#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
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#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
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#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
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#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
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2012-09-19 11:52:12 +08:00
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#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
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#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
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#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
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2012-06-05 23:23:08 +08:00
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 64
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2012-09-19 11:52:12 +08:00
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#ifdef CONFIG_M5249
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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#else
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2012-06-05 23:23:08 +08:00
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#define MCFGPIO_IRQ_MAX 7
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#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
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2012-09-19 11:52:12 +08:00
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#endif
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/****************************************************************************/
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#ifdef __ASSEMBLER__
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#ifdef CONFIG_M5249C3
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/*
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* The M5249C3 board needs a little help getting all its SIM devices
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* initialized at kernel start time. dBUG doesn't set much up, so
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* we need to do it manually.
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*/
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.macro m5249c3_setup
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/*
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* Set MBAR1 and MBAR2, just incase they are not set.
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*/
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movel #0x10000001,%a0
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movec %a0,%MBAR /* map MBAR region */
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subql #1,%a0 /* get MBAR address in a0 */
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movel #0x80000001,%a1
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movec %a1,#3086 /* map MBAR2 region */
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subql #1,%a1 /* get MBAR2 address in a1 */
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/*
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* Move secondary interrupts to their base (128).
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*/
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moveb #MCFINTC2_VECBASE,%d0
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moveb %d0,0x16b(%a1) /* interrupt base register */
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/*
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* Work around broken CSMR0/DRAM vector problem.
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*/
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movel #0x001F0021,%d0 /* disable C/I bit */
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movel %d0,0x84(%a0) /* set CSMR0 */
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/*
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* Disable the PLL firstly. (Who knows what state it is
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* in here!).
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*/
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movel 0x180(%a1),%d0 /* get current PLL value */
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andl #0xfffffffe,%d0 /* PLL bypass first */
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movel %d0,0x180(%a1) /* set PLL register */
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nop
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#if CONFIG_CLOCK_FREQ == 140000000
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/*
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* Set initial clock frequency. This assumes M5249C3 board
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* is fitted with 11.2896MHz crystal. It will program the
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* PLL for 140MHz. Lets go fast :-)
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*/
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movel #0x125a40f0,%d0 /* set for 140MHz */
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movel %d0,0x180(%a1) /* set PLL register */
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orl #0x1,%d0
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movel %d0,0x180(%a1) /* set PLL register */
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#endif
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/*
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* Setup CS1 for ethernet controller.
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* (Setup as per M5249C3 doco).
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*/
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movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
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movel %d0,0x8c(%a0)
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movel #0x001f0021,%d0 /* CS1 size of 1Mb */
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movel %d0,0x90(%a0)
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movew #0x0080,%d0 /* CS1 = 16bit port, AA */
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movew %d0,0x96(%a0)
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/*
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* Setup CS2 for IDE interface.
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*/
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movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
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movel %d0,0x98(%a0)
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movel #0x001f0001,%d0 /* CS2 size of 1MB */
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movel %d0,0x9c(%a0)
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movew #0x0080,%d0 /* CS2 = 16bit, TA */
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movew %d0,0xa2(%a0)
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movel #0x00107000,%d0 /* IDEconfig1 */
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movel %d0,0x18c(%a1)
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movel #0x000c0400,%d0 /* IDEconfig2 */
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movel %d0,0x190(%a1)
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movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
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orl %d0,0xc(%a1) /* function GPIO19 */
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orl %d0,0x8(%a1) /* enable GPIO19 as output */
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orl %d0,0x4(%a1) /* de-assert IDE reset */
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.endm
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#define PLATFORM_SETUP m5249c3_setup
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2012-06-05 23:23:08 +08:00
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2012-09-19 11:52:12 +08:00
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#endif /* CONFIG_M5249C3 */
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#endif /* __ASSEMBLER__ */
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2012-06-05 23:23:08 +08:00
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/****************************************************************************/
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#endif /* m525xsim_h */
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