forked from luck/tmp_suning_uos_patched
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
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/*
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* arch/sh/mm/cache-sh2.c
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*
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* Copyright (C) 2002 Paul Mundt
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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#include <asm/addrspace.h>
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#include <asm/processor.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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/*
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* Calculate the OC address and set the way bit on the SH-2.
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*
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* We must have already jump_to_P2()'ed prior to calling this
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* function, since we rely on CCR manipulation to do the
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* Right Thing(tm).
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*/
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unsigned long __get_oc_addr(unsigned long set, unsigned long way)
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{
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unsigned long ccr;
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/*
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* On SH-2 the way bit isn't tracked in the address field
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* if we're doing address array access .. instead, we need
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* to manually switch out the way in the CCR.
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*/
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ccr = ctrl_inl(CCR);
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ccr &= ~0x00c0;
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ccr |= way << cpu_data->dcache.way_shift;
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/*
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* Despite the number of sets being halved, we end up losing
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* the first 2 ways to OCRAM instead of the last 2 (if we're
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* 4-way). As a result, forcibly setting the W1 bit handily
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* bumps us up 2 ways.
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*/
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if (ccr & CCR_CACHE_ORA)
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ccr |= 1 << (cpu_data->dcache.way_shift + 1);
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ctrl_outl(ccr, CCR);
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return CACHE_OC_ADDRESS_ARRAY | (set << cpu_data->dcache.entry_shift);
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}
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