forked from luck/tmp_suning_uos_patched
70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
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/*
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* linux/include/asm-arm/arch-ebsa285/system.h
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*
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* Copyright (C) 1996-1999 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/hardware/dec21285.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/leds.h>
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#include <asm/mach-types.h>
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static inline void arch_idle(void)
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{
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cpu_do_idle();
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}
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static inline void arch_reset(char mode)
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{
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if (mode == 's') {
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/*
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* Jump into the ROM
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*/
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cpu_reset(0x41000000);
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} else {
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if (machine_is_netwinder()) {
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/* open up the SuperIO chip
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*/
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outb(0x87, 0x370);
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outb(0x87, 0x370);
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/* aux function group 1 (logical device 7)
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*/
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outb(0x07, 0x370);
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outb(0x07, 0x371);
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/* set GP16 for WD-TIMER output
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*/
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outb(0xe6, 0x370);
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outb(0x00, 0x371);
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/* set a RED LED and toggle WD_TIMER for rebooting
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*/
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outb(0xc4, 0x338);
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} else {
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/*
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* Force the watchdog to do a CPU reset.
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*
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* After making sure that the watchdog is disabled
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* (so we can change the timer registers) we first
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* enable the timer to autoreload itself. Next, the
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* timer interval is set really short and any
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* current interrupt request is cleared (so we can
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* see an edge transition). Finally, TIMER4 is
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* enabled as the watchdog.
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*/
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*CSR_SA110_CNTL &= ~(1 << 13);
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*CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
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TIMER_CNTL_AUTORELOAD |
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TIMER_CNTL_DIV16;
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*CSR_TIMER4_LOAD = 0x2;
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*CSR_TIMER4_CLR = 0;
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*CSR_SA110_CNTL |= (1 << 13);
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}
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}
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}
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