[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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/*
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* include/asm-arm/arch-orion/orion.h
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*
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* Generic definitions of Orion SoC flavors:
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* Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION_H__
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#define __ASM_ARCH_ORION_H__
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/*******************************************************************************
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* Orion Address Map
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* Use the same mapping (1:1 virtual:physical) of internal registers and
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* PCI system (PCI+PCIE) for all machines.
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* Each machine defines the rest of its mapping (e.g. device bus flashes)
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******************************************************************************/
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#define ORION_REGS_BASE 0xf1000000
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#define ORION_REGS_SIZE SZ_1M
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#define ORION_PCI_SYS_MEM_BASE 0xe0000000
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#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
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#define ORION_PCIE_MEM_SIZE SZ_128M
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#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
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#define ORION_PCI_MEM_SIZE SZ_128M
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#define ORION_PCI_SYS_IO_BASE 0xf2000000
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#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
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#define ORION_PCIE_IO_SIZE SZ_1M
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#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
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#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
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#define ORION_PCI_IO_SIZE SZ_1M
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#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
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/* Relevant only for Orion-NAS */
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#define ORION_PCIE_WA_BASE 0xf0000000
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#define ORION_PCIE_WA_SIZE SZ_16M
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/*******************************************************************************
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* Supported Devices & Revisions
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******************************************************************************/
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2007-11-11 19:05:11 +08:00
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/* Orion-1 (88F5181) */
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#define MV88F5181_DEV_ID 0x5181
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#define MV88F5181_REV_B1 3
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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/*******************************************************************************
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* Orion Registers Map
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******************************************************************************/
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#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
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#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
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#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
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#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
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#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
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#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
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#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
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#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
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#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
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#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
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#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
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#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
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#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
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#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
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#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
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#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
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#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
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#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
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/*******************************************************************************
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* Device Bus Registers
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******************************************************************************/
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#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
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#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
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#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
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#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
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#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
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#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
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#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
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#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
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#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
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#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
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#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
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#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
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#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
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#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
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#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
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#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
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#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
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#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
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#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
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#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
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#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
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#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
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#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
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#define GPIO_MAX 32
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/***************************************************************************
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* Orion CPU Bridge Registers
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**************************************************************************/
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#define CPU_CONF ORION_BRIDGE_REG(0x100)
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#define CPU_CTRL ORION_BRIDGE_REG(0x104)
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#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
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#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
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#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
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#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
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#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
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#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
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#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
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#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
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#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
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#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
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#ifndef __ASSEMBLY__
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/*******************************************************************************
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* Helpers to access Orion registers
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******************************************************************************/
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#include <asm/types.h>
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#include <asm/io.h>
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#define orion_read(r) __raw_readl(r)
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#define orion_write(r, val) __raw_writel(val, r)
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/*
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* These are not preempt safe. Locks, if needed, must be taken care by caller.
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*/
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#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
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#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_ORION_H__ */
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