forked from luck/tmp_suning_uos_patched
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
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/*
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* linux/arch/arm/mach-epxa10db/irq.c
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*
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* Copyright (C) 2001 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/stddef.h>
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#include <linux/timer.h>
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#include <linux/list.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/platform.h>
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#include <asm/arch/int_ctrl00.h>
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static void epxa_mask_irq(unsigned int irq)
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{
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writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
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}
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static void epxa_unmask_irq(unsigned int irq)
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{
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writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
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}
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static struct irqchip epxa_irq_chip = {
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.ack = epxa_mask_irq,
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.mask = epxa_mask_irq,
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.unmask = epxa_unmask_irq,
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};
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static struct resource irq_resource = {
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.name = "irq_handler",
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.start = IO_ADDRESS(EXC_INT_CTRL00_BASE),
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.end = IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4,
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};
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void __init epxa10db_init_irq(void)
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{
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unsigned int i;
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request_resource(&iomem_resource, &irq_resource);
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/*
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* This bit sets up the interrupt controller using
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* the 6 PLD interrupts mode (the default) each
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* irqs is assigned a priority which is the same
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* as its interrupt number. This scheme is used because
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* its easy, but you may want to change it depending
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* on the contents of your PLD
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*/
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writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
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for (i = 0; i < NR_IRQS; i++){
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writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
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set_irq_chip(i,&epxa_irq_chip);
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set_irq_handler(i,do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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/* Disable all interrupts */
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writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
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}
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