2018-08-22 06:02:17 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2011-03-23 19:42:44 +08:00
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/*
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2017-05-10 17:25:25 +08:00
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* Driver for the MMC / SD / SDIO cell found in:
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*
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* TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
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2011-03-23 19:42:44 +08:00
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*
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2019-03-15 06:54:41 +08:00
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* Copyright (C) 2015-19 Renesas Electronics Corporation
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* Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
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2017-05-30 20:50:52 +08:00
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* Copyright (C) 2016-17 Horms Solutions, Simon Horman
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2011-03-23 19:42:44 +08:00
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* Copyright (C) 2007 Ian Molton
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* Copyright (C) 2004 Ian Molton
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*/
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#ifndef TMIO_MMC_H
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#define TMIO_MMC_H
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2015-01-13 12:59:14 +08:00
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#include <linux/dmaengine.h>
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2011-03-23 19:42:44 +08:00
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#include <linux/highmem.h>
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2011-07-14 18:12:38 +08:00
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#include <linux/mutex.h>
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2011-03-23 19:42:44 +08:00
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#include <linux/pagemap.h>
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2011-07-27 02:50:23 +08:00
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#include <linux/scatterlist.h>
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2012-01-06 20:06:51 +08:00
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#include <linux/spinlock.h>
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2016-12-30 20:47:23 +08:00
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#include <linux/interrupt.h>
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2011-03-23 19:42:44 +08:00
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2016-04-26 23:55:26 +08:00
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#define CTL_SD_CMD 0x00
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#define CTL_ARG_REG 0x04
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#define CTL_STOP_INTERNAL_ACTION 0x08
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#define CTL_XFER_BLK_COUNT 0xa
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#define CTL_RESPONSE 0x0c
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2016-04-28 00:51:27 +08:00
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/* driver merges STATUS and following STATUS2 */
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2016-04-26 23:55:26 +08:00
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#define CTL_STATUS 0x1c
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2016-04-28 00:51:27 +08:00
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/* driver merges IRQ_MASK and following IRQ_MASK2 */
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2016-04-26 23:55:26 +08:00
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#define CTL_IRQ_MASK 0x20
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#define CTL_SD_CARD_CLK_CTL 0x24
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#define CTL_SD_XFER_LEN 0x26
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#define CTL_SD_MEM_CARD_OPT 0x28
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#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
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#define CTL_SD_DATA_PORT 0x30
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#define CTL_TRANSACTION_CTL 0x34
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#define CTL_SDIO_STATUS 0x36
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#define CTL_SDIO_IRQ_MASK 0x38
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#define CTL_DMA_ENABLE 0xd8
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#define CTL_RESET_SD 0xe0
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#define CTL_VERSION 0xe2
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2018-06-18 20:57:50 +08:00
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#define CTL_SDIF_MODE 0xe6
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2016-04-26 23:55:26 +08:00
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2017-03-14 18:09:16 +08:00
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/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
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#define TMIO_STOP_STP BIT(0)
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#define TMIO_STOP_SEC BIT(8)
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2017-03-14 18:09:17 +08:00
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/* Definitions for values the CTL_STATUS register can take */
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2016-04-28 00:51:24 +08:00
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#define TMIO_STAT_CMDRESPEND BIT(0)
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#define TMIO_STAT_DATAEND BIT(2)
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#define TMIO_STAT_CARD_REMOVE BIT(3)
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#define TMIO_STAT_CARD_INSERT BIT(4)
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#define TMIO_STAT_SIGSTATE BIT(5)
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#define TMIO_STAT_WRPROTECT BIT(7)
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#define TMIO_STAT_CARD_REMOVE_A BIT(8)
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#define TMIO_STAT_CARD_INSERT_A BIT(9)
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#define TMIO_STAT_SIGSTATE_A BIT(10)
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2017-03-14 18:09:17 +08:00
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/* These belong technically to CTL_STATUS2, but the driver merges them */
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2016-04-28 00:51:24 +08:00
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#define TMIO_STAT_CMD_IDX_ERR BIT(16)
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#define TMIO_STAT_CRCFAIL BIT(17)
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#define TMIO_STAT_STOPBIT_ERR BIT(18)
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#define TMIO_STAT_DATATIMEOUT BIT(19)
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#define TMIO_STAT_RXOVERFLOW BIT(20)
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#define TMIO_STAT_TXUNDERRUN BIT(21)
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#define TMIO_STAT_CMDTIMEOUT BIT(22)
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2016-04-28 00:51:25 +08:00
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#define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
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2016-04-28 00:51:24 +08:00
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#define TMIO_STAT_RXRDY BIT(24)
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#define TMIO_STAT_TXRQ BIT(25)
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2018-11-19 21:13:57 +08:00
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#define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */
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2016-04-28 00:51:26 +08:00
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#define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
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#define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
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2016-04-28 00:51:24 +08:00
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#define TMIO_STAT_CMD_BUSY BIT(30)
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#define TMIO_STAT_ILL_ACCESS BIT(31)
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2016-04-26 23:55:26 +08:00
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2017-06-30 18:56:47 +08:00
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/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
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2016-04-26 23:55:26 +08:00
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#define CLK_CTL_DIV_MASK 0xff
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#define CLK_CTL_SCLKEN BIT(8)
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2017-06-30 18:56:47 +08:00
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/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
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2016-09-20 04:57:48 +08:00
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#define CARD_OPT_WIDTH8 BIT(13)
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#define CARD_OPT_WIDTH BIT(15)
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2017-03-14 18:09:17 +08:00
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/* Definitions for values the CTL_SDIO_STATUS register can take */
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2011-03-24 16:48:36 +08:00
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#define TMIO_SDIO_STAT_IOIRQ 0x0001
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2011-03-23 19:42:44 +08:00
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#define TMIO_SDIO_STAT_EXPUB52 0x4000
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2011-03-24 16:48:36 +08:00
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#define TMIO_SDIO_STAT_EXWT 0x8000
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#define TMIO_SDIO_MASK_ALL 0xc007
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2011-03-23 19:42:44 +08:00
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2017-01-20 04:07:18 +08:00
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#define TMIO_SDIO_SETBITS_MASK 0x0006
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2017-06-30 18:56:48 +08:00
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/* Definitions for values the CTL_DMA_ENABLE register can take */
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#define DMA_ENABLE_DMASDRW BIT(1)
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2011-03-23 19:42:44 +08:00
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/* Define some IRQ masks */
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/* This is the mask used at reset by the chip */
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2018-11-27 01:02:47 +08:00
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#define TMIO_MASK_INIT_RCAR2 0x8b7f031d /* Initial value for R-Car Gen2+ */
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2011-03-23 19:42:44 +08:00
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#define TMIO_MASK_ALL 0x837f031d
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#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
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#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
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#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
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TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
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#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
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2019-03-15 06:31:29 +08:00
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#define TMIO_MAX_BLK_SIZE 512
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2011-03-23 19:42:44 +08:00
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struct tmio_mmc_data;
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2015-01-13 12:59:05 +08:00
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struct tmio_mmc_host;
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2011-03-23 19:42:44 +08:00
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2017-05-10 17:25:26 +08:00
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struct tmio_mmc_dma_ops {
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void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
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void (*enable)(struct tmio_mmc_host *host, bool enable);
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void (*request)(struct tmio_mmc_host *host,
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struct tmio_mmc_data *pdata);
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void (*release)(struct tmio_mmc_host *host);
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void (*abort)(struct tmio_mmc_host *host);
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2017-06-21 22:00:28 +08:00
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void (*dataend)(struct tmio_mmc_host *host);
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2017-05-10 17:25:26 +08:00
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};
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2011-03-23 19:42:44 +08:00
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struct tmio_mmc_host {
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void __iomem *ctl;
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struct mmc_command *cmd;
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struct mmc_request *mrq;
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struct mmc_data *data;
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struct mmc_host *mmc;
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2017-11-25 00:24:41 +08:00
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struct mmc_host_ops ops;
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2011-03-23 19:42:44 +08:00
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/* Callbacks for clock / power control */
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void (*set_pwr)(struct platform_device *host, int state);
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/* pio related stuff */
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struct scatterlist *sg_ptr;
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struct scatterlist *sg_orig;
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unsigned int sg_len;
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unsigned int sg_off;
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2017-11-25 00:24:50 +08:00
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unsigned int bus_shift;
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2011-03-23 19:42:44 +08:00
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struct platform_device *pdev;
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struct tmio_mmc_data *pdata;
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/* DMA support */
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2018-10-12 23:03:08 +08:00
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bool dma_on;
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2011-03-23 19:42:44 +08:00
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struct dma_chan *chan_rx;
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struct dma_chan *chan_tx;
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struct tasklet_struct dma_issue;
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struct scatterlist bounce_sg;
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u8 *bounce_buf;
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/* Track lost interrupts */
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struct delayed_work delayed_reset_work;
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2011-07-14 18:12:38 +08:00
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struct work_struct done;
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2013-10-30 07:16:17 +08:00
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/* Cache */
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2011-08-25 09:27:25 +08:00
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u32 sdcard_irq_mask;
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u32 sdio_irq_mask;
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2013-10-30 07:16:17 +08:00
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unsigned int clk_cache;
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2018-11-19 21:13:57 +08:00
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u32 sdcard_irq_setbit_mask;
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2011-08-25 09:27:25 +08:00
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2011-07-14 18:12:38 +08:00
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spinlock_t lock; /* protect host private data */
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2011-03-23 19:42:44 +08:00
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unsigned long last_req_ts;
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2011-07-14 18:12:38 +08:00
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struct mutex ios_lock; /* protect set_ios() context */
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2012-02-10 05:57:08 +08:00
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bool native_hotplug;
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2013-10-24 21:58:45 +08:00
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bool sdio_irq_enabled;
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2015-01-13 12:57:42 +08:00
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2016-11-03 22:16:01 +08:00
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/* Mandatory callback */
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2016-04-01 23:44:31 +08:00
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int (*clk_enable)(struct tmio_mmc_host *host);
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2018-08-23 12:44:16 +08:00
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void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
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2016-11-03 22:16:01 +08:00
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/* Optional callbacks */
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2016-04-01 23:44:31 +08:00
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void (*clk_disable)(struct tmio_mmc_host *host);
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2015-01-13 12:58:10 +08:00
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int (*multi_io_quirk)(struct mmc_card *card,
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unsigned int direction, int blk_size);
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2016-11-03 22:16:01 +08:00
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int (*write16_hook)(struct tmio_mmc_host *host, int addr);
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2018-10-10 11:51:31 +08:00
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void (*reset)(struct tmio_mmc_host *host);
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2016-11-03 22:16:02 +08:00
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void (*hw_reset)(struct tmio_mmc_host *host);
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2020-01-30 04:37:06 +08:00
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bool (*check_retune)(struct tmio_mmc_host *host);
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2016-11-03 22:16:03 +08:00
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/*
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* Mandatory callback for tuning to occur which is optional for SDR50
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* and mandatory for SDR104.
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*/
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2020-01-30 04:37:04 +08:00
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int (*execute_tuning)(struct tmio_mmc_host *host, u32 opcode);
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2016-11-03 22:16:03 +08:00
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2018-06-18 20:57:50 +08:00
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void (*prepare_hs400_tuning)(struct tmio_mmc_host *host);
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void (*hs400_downgrade)(struct tmio_mmc_host *host);
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void (*hs400_complete)(struct tmio_mmc_host *host);
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2017-05-10 17:25:26 +08:00
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const struct tmio_mmc_dma_ops *dma_ops;
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2011-03-23 19:42:44 +08:00
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};
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2018-01-18 00:28:02 +08:00
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struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
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struct tmio_mmc_data *pdata);
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2015-01-13 12:57:22 +08:00
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void tmio_mmc_host_free(struct tmio_mmc_host *host);
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2018-01-18 00:28:04 +08:00
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int tmio_mmc_host_probe(struct tmio_mmc_host *host);
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2011-03-23 19:42:44 +08:00
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void tmio_mmc_host_remove(struct tmio_mmc_host *host);
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void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
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void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
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void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
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2011-05-06 19:02:33 +08:00
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irqreturn_t tmio_mmc_irq(int irq, void *devid);
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2011-03-23 19:42:44 +08:00
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static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
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unsigned long *flags)
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{
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local_irq_save(*flags);
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2011-11-27 13:27:00 +08:00
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return kmap_atomic(sg_page(sg)) + sg->offset;
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2011-03-23 19:42:44 +08:00
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}
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static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
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unsigned long *flags, void *virt)
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{
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2011-11-27 13:27:00 +08:00
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kunmap_atomic(virt - sg->offset);
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2011-03-23 19:42:44 +08:00
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local_irq_restore(*flags);
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}
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2014-08-25 18:03:20 +08:00
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#ifdef CONFIG_PM
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2011-05-12 00:51:11 +08:00
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int tmio_mmc_host_runtime_suspend(struct device *dev);
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int tmio_mmc_host_runtime_resume(struct device *dev);
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2013-10-23 20:55:07 +08:00
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#endif
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2011-05-12 00:51:11 +08:00
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2011-06-21 07:00:09 +08:00
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static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
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{
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2017-12-19 21:34:03 +08:00
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return ioread16(host->ctl + (addr << host->bus_shift));
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2011-06-21 07:00:09 +08:00
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}
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static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
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2017-06-17 00:11:03 +08:00
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u16 *buf, int count)
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2011-06-21 07:00:09 +08:00
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{
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2017-12-18 08:00:21 +08:00
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ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
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2011-06-21 07:00:09 +08:00
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}
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2017-06-17 00:11:03 +08:00
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static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
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int addr)
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2011-06-21 07:00:09 +08:00
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{
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2017-12-19 21:34:03 +08:00
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return ioread16(host->ctl + (addr << host->bus_shift)) |
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ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
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2011-06-21 07:00:09 +08:00
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}
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2016-09-12 22:15:06 +08:00
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static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
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2017-06-17 00:11:03 +08:00
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u32 *buf, int count)
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2016-09-12 22:15:06 +08:00
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{
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2017-12-18 08:00:21 +08:00
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ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
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2016-09-12 22:15:06 +08:00
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}
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2017-06-17 00:11:03 +08:00
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static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
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u16 val)
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2011-06-21 07:00:09 +08:00
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{
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2011-06-21 07:00:10 +08:00
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/* If there is a hook and it returns non-zero then there
|
|
|
|
* is an error and the write should be skipped
|
|
|
|
*/
|
2015-01-13 12:57:42 +08:00
|
|
|
if (host->write16_hook && host->write16_hook(host, addr))
|
2011-06-21 07:00:10 +08:00
|
|
|
return;
|
2017-12-19 21:34:03 +08:00
|
|
|
iowrite16(val, host->ctl + (addr << host->bus_shift));
|
2011-06-21 07:00:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
|
2017-06-17 00:11:03 +08:00
|
|
|
u16 *buf, int count)
|
2011-06-21 07:00:09 +08:00
|
|
|
{
|
2017-12-18 08:00:21 +08:00
|
|
|
iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
|
2011-06-21 07:00:09 +08:00
|
|
|
}
|
|
|
|
|
2017-06-17 00:11:03 +08:00
|
|
|
static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
|
|
|
|
int addr, u32 val)
|
2011-06-21 07:00:09 +08:00
|
|
|
{
|
2018-11-19 21:13:57 +08:00
|
|
|
if (addr == CTL_IRQ_MASK || addr == CTL_STATUS)
|
|
|
|
val |= host->sdcard_irq_setbit_mask;
|
|
|
|
|
2017-12-19 21:34:03 +08:00
|
|
|
iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
|
|
|
|
iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
|
2011-06-21 07:00:09 +08:00
|
|
|
}
|
|
|
|
|
mmc: tmio: fix access width of Block Count Register
In R-Car Gen2 or later, the maximum number of transfer blocks are
changed from 0xFFFF to 0xFFFFFFFF. Therefore, Block Count Register
should use iowrite32().
If another system (U-boot, Hypervisor OS, etc) uses bit[31:16], this
value will not be cleared. So, SD/MMC card initialization fails.
So, check for the bigger register and use apropriate write. Also, mark
the register as extended on Gen2.
Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
[wsa: use max_blk_count in if(), add Gen2, update commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: stable@kernel.org
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
[Ulf: Fixed build error]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-22 03:38:05 +08:00
|
|
|
static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
|
|
|
|
{
|
|
|
|
iowrite32(val, host->ctl + (addr << host->bus_shift));
|
|
|
|
}
|
|
|
|
|
2016-09-12 22:15:06 +08:00
|
|
|
static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
|
2017-06-17 00:11:03 +08:00
|
|
|
const u32 *buf, int count)
|
2016-09-12 22:15:06 +08:00
|
|
|
{
|
2017-12-18 08:00:21 +08:00
|
|
|
iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
|
2016-09-12 22:15:06 +08:00
|
|
|
}
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
#endif
|