2016-07-06 14:31:34 +08:00
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/*
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* Copyright 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_SUN50I_A64_H_
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#define _CCU_SUN50I_A64_H_
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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#define CLK_OSC_12M 0
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#define CLK_PLL_CPUX 1
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#define CLK_PLL_AUDIO_BASE 2
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#define CLK_PLL_AUDIO 3
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#define CLK_PLL_AUDIO_2X 4
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#define CLK_PLL_AUDIO_4X 5
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#define CLK_PLL_AUDIO_8X 6
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#define CLK_PLL_VIDEO0 7
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VE 9
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#define CLK_PLL_DDR0 10
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2017-05-31 15:58:23 +08:00
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/* PLL_PERIPH0 exported for PRCM */
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2016-07-06 14:31:34 +08:00
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#define CLK_PLL_PERIPH0_2X 12
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#define CLK_PLL_PERIPH1 13
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#define CLK_PLL_PERIPH1_2X 14
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#define CLK_PLL_VIDEO1 15
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#define CLK_PLL_GPU 16
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#define CLK_PLL_MIPI 17
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#define CLK_PLL_HSIC 18
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#define CLK_PLL_DE 19
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#define CLK_PLL_DDR1 20
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#define CLK_CPUX 21
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#define CLK_AXI 22
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#define CLK_APB 23
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#define CLK_AHB1 24
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#define CLK_APB1 25
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#define CLK_APB2 26
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#define CLK_AHB2 27
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/* All the bus gates are exported */
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/* The first bunch of module clocks are exported */
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#define CLK_USB_OHCI0_12M 90
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#define CLK_USB_OHCI1_12M 92
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#define CLK_DRAM 94
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_MBUS 112
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/* And the DSI and GPU module clock is exported */
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#define CLK_NUMBER (CLK_GPU + 1)
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#endif /* _CCU_SUN50I_A64_H_ */
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