forked from luck/tmp_suning_uos_patched
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
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/*
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* arch/mips/ddb5xxx/common/nile4.c
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* misc low-level routines for vrc-5xxx controllers.
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*
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* derived from original code by Geert Uytterhoeven <geert@sonycom.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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u32
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ddb_calc_pdar(u32 phys, u32 size, int width,
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int on_memory_bus, int pci_visible)
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{
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u32 maskbits;
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u32 widthbits;
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switch (size) {
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#if 0 /* We don't support 4 GB yet */
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case 0x100000000: /* 4 GB */
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maskbits = 4;
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break;
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#endif
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case 0x80000000: /* 2 GB */
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maskbits = 5;
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break;
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case 0x40000000: /* 1 GB */
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maskbits = 6;
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break;
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case 0x20000000: /* 512 MB */
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maskbits = 7;
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break;
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case 0x10000000: /* 256 MB */
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maskbits = 8;
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break;
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case 0x08000000: /* 128 MB */
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maskbits = 9;
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break;
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case 0x04000000: /* 64 MB */
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maskbits = 10;
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break;
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case 0x02000000: /* 32 MB */
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maskbits = 11;
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break;
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case 0x01000000: /* 16 MB */
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maskbits = 12;
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break;
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case 0x00800000: /* 8 MB */
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maskbits = 13;
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break;
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case 0x00400000: /* 4 MB */
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maskbits = 14;
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break;
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case 0x00200000: /* 2 MB */
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maskbits = 15;
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break;
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case 0: /* OFF */
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maskbits = 0;
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break;
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default:
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panic("nile4_set_pdar: unsupported size %p", (void *) size);
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}
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switch (width) {
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case 8:
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widthbits = 0;
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break;
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case 16:
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widthbits = 1;
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break;
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case 32:
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widthbits = 2;
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break;
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case 64:
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widthbits = 3;
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break;
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default:
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panic("nile4_set_pdar: unsupported width %d", width);
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}
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return maskbits | (on_memory_bus ? 0x10 : 0) |
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(pci_visible ? 0x20 : 0) | (widthbits << 6) |
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(phys & 0xffe00000);
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}
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void
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ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
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int on_memory_bus, int pci_visible)
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{
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u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible);
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ddb_out32(pdar, temp);
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ddb_out32(pdar + 4, 0);
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/*
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* When programming a PDAR, the register should be read immediately
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* after writing it. This ensures that address decoders are properly
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* configured.
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* [jsun] is this really necessary?
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*/
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ddb_in32(pdar);
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ddb_in32(pdar + 4);
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}
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/*
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* routines that mess with PCIINITx registers
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*/
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void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
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{
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switch (type) {
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case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */
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case DDB_PCICMD_IO: /* PCI I/O Space */
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case DDB_PCICMD_MEM: /* PCI Memory Space */
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case DDB_PCICMD_CFG: /* PCI Configuration Space */
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break;
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default:
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panic("nile4_set_pmr: invalid type %d", type);
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}
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ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
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ddb_out32(pmr + 4, 0);
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}
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