forked from luck/tmp_suning_uos_patched
75 lines
2.8 KiB
C
75 lines
2.8 KiB
C
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/*
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* include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2
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* cache memories
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*
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* Copyright (C) 2003 NEC Electronics Corporation
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* Copyright (C) 2003 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_V850E2_CACHE_H__
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#define __V850_V850E2_CACHE_H__
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#include <asm/types.h>
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/* Cache control registers. */
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/* Bus Transaction Control */
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#define V850E2_CACHE_BTSC_ADDR 0xFFFFF070
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#define V850E2_CACHE_BTSC (*(volatile u16 *)V850E2_CACHE_BTSC_ADDR)
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#define V850E2_CACHE_BTSC_ICM 0x0001 /* icache enable */
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#define V850E2_CACHE_BTSC_DCM0 0x0004 /* dcache enable, bit 0 */
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#define V850E2_CACHE_BTSC_DCM1 0x0008 /* dcache enable, bit 1 */
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#define V850E2_CACHE_BTSC_DCM_WT /* write-through */ \
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V850E2_CACHE_BTSC_DCM0
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#ifdef CONFIG_V850E2_V850E2S
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# define V850E2_CACHE_BTSC_DCM_WB_NO_ALLOC /* write-back, non-alloc */ \
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V850E2_CACHE_BTSC_DCM1
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# define V850E2_CACHE_BTSC_DCM_WB_ALLOC /* write-back, non-alloc */ \
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(V850E2_CACHE_BTSC_DCM1 | V850E2_CACHE_BTSC_DCM0)
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# define V850E2_CACHE_BTSC_ISEQ 0x0010 /* icache `address sequence mode' */
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# define V850E2_CACHE_BTSC_DSEQ 0x0020 /* dcache `address sequence mode' */
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# define V850E2_CACHE_BTSC_IRFC 0x0030
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# define V850E2_CACHE_BTSC_ILCD 0x4000
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# define V850E2_CACHE_BTSC_VABE 0x8000
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#endif /* CONFIG_V850E2_V850E2S */
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/* Cache operation start address register (low-bits). */
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#define V850E2_CACHE_CADL_ADDR 0xFFFFF074
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#define V850E2_CACHE_CADL (*(volatile u16 *)V850E2_CACHE_CADL_ADDR)
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/* Cache operation start address register (high-bits). */
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#define V850E2_CACHE_CADH_ADDR 0xFFFFF076
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#define V850E2_CACHE_CADH (*(volatile u16 *)V850E2_CACHE_CADH_ADDR)
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/* Cache operation count register. */
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#define V850E2_CACHE_CCNT_ADDR 0xFFFFF078
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#define V850E2_CACHE_CCNT (*(volatile u16 *)V850E2_CACHE_CCNT_ADDR)
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/* Cache operation specification register. */
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#define V850E2_CACHE_COPR_ADDR 0xFFFFF07A
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#define V850E2_CACHE_COPR (*(volatile u16 *)V850E2_CACHE_COPR_ADDR)
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#define V850E2_CACHE_COPR_STRT 0x0001 /* start cache operation */
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#define V850E2_CACHE_COPR_LBSL 0x0100 /* 0 = icache, 1 = dcache */
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#define V850E2_CACHE_COPR_WSLE 0x0200 /* operate on cache way */
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#define V850E2_CACHE_COPR_WSL(way) ((way) * 0x0400) /* way select */
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#define V850E2_CACHE_COPR_CFC(op) ((op) * 0x1000) /* cache function code */
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/* Size of a cache line in bytes. */
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#define V850E2_CACHE_LINE_SIZE_BITS 4
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#define V850E2_CACHE_LINE_SIZE (1 << V850E2_CACHE_LINE_SIZE_BITS)
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/* The size of each cache `way' in lines. */
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#define V850E2_CACHE_WAY_SIZE 256
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/* For <asm/cache.h> */
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#define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE
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#endif /* __V850_V850E2_CACHE_H__ */
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