2005-04-17 06:20:36 +08:00
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#
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# Library configuration
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#
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2009-03-07 00:21:46 +08:00
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config BINARY_PRINTF
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def_bool n
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2005-04-17 06:20:36 +08:00
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menu "Library routines"
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2009-07-13 18:35:12 +08:00
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config RAID6_PQ
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tristate
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2006-12-08 18:36:25 +08:00
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config BITREVERSE
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tristate
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2014-11-03 10:01:03 +08:00
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config HAVE_ARCH_BITREVERSE
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2015-02-17 08:00:20 +08:00
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bool
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2014-11-03 10:01:03 +08:00
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default n
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depends on BITREVERSE
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help
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2015-04-17 03:49:07 +08:00
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This option enables the use of hardware bit-reversal instructions on
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architectures which support such operations.
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2014-11-03 10:01:03 +08:00
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2009-06-11 21:51:15 +08:00
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config RATIONAL
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2014-12-21 04:41:11 +08:00
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bool
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2009-06-11 21:51:15 +08:00
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2012-05-25 04:12:28 +08:00
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config GENERIC_STRNCPY_FROM_USER
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bool
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2012-05-27 02:06:38 +08:00
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config GENERIC_STRNLEN_USER
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bool
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2013-06-05 00:46:26 +08:00
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config GENERIC_NET_UTILS
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bool
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2008-04-25 19:12:53 +08:00
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config GENERIC_FIND_FIRST_BIT
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2008-10-16 13:01:38 +08:00
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bool
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2008-04-25 19:12:53 +08:00
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2012-01-30 06:20:48 +08:00
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config NO_GENERIC_PCI_IOPORT_MAP
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bool
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2011-11-25 02:45:20 +08:00
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config GENERIC_PCI_IOMAP
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bool
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2011-11-24 20:54:28 +08:00
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config GENERIC_IOMAP
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bool
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2011-11-25 02:45:20 +08:00
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select GENERIC_PCI_IOMAP
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2011-11-24 20:54:28 +08:00
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2012-02-07 08:22:46 +08:00
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config GENERIC_IO
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2014-12-21 04:41:11 +08:00
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bool
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2012-02-07 08:22:46 +08:00
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default n
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lib: add support for stmp-style devices
MX23/28 use IP cores which follow a register layout I have first seen on
STMP3xxx SoCs. In this layout, every register actually has four u32:
1.) to store a value directly
2.) a SET register where every 1-bit sets the corresponding bit,
others are unaffected
3.) same with a CLR register
4.) same with a TOG (toggle) register
Also, the 2 MSBs in register 0 are always the same and can be used to reset
the IP core.
All this is strictly speaking not mach-specific (but IP core specific) and,
thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores
following this stmp-style. So:
Introduce a stmp-style device, put the code and defines for that in a public
place (lib/), and let drivers for stmp-style devices select that code.
To avoid regressions and ease reviewing, the actual code is simply copied from
mach-mxs. It definately wants updates, but those need a seperate patch series.
Voila, mach dependency gone, reusable code introduced. Note that I didn't
remove the duplicated code from mach-mxs yet, first the drivers have to be
converted.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
2011-09-01 02:35:40 +08:00
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config STMP_DEVICE
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bool
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2012-12-18 08:01:39 +08:00
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lockref: implement lockless reference count updates using cmpxchg()
Instead of taking the spinlock, the lockless versions atomically check
that the lock is not taken, and do the reference count update using a
cmpxchg() loop. This is semantically identical to doing the reference
count update protected by the lock, but avoids the "wait for lock"
contention that you get when accesses to the reference count are
contended.
Note that a "lockref" is absolutely _not_ equivalent to an atomic_t.
Even when the lockref reference counts are updated atomically with
cmpxchg, the fact that they also verify the state of the spinlock means
that the lockless updates can never happen while somebody else holds the
spinlock.
So while "lockref_put_or_lock()" looks a lot like just another name for
"atomic_dec_and_lock()", and both optimize to lockless updates, they are
fundamentally different: the decrement done by atomic_dec_and_lock() is
truly independent of any lock (as long as it doesn't decrement to zero),
so a locked region can still see the count change.
The lockref structure, in contrast, really is a *locked* reference
count. If you hold the spinlock, the reference count will be stable and
you can modify the reference count without using atomics, because even
the lockless updates will see and respect the state of the lock.
In order to enable the cmpxchg lockless code, the architecture needs to
do three things:
(1) Make sure that the "arch_spinlock_t" and an "unsigned int" can fit
in an aligned u64, and have a "cmpxchg()" implementation that works
on such a u64 data type.
(2) define a helper function to test for a spinlock being unlocked
("arch_spin_value_unlocked()")
(3) select the "ARCH_USE_CMPXCHG_LOCKREF" config variable in its
Kconfig file.
This enables it for x86-64 (but not 32-bit, we'd need to make sure
cmpxchg() turns into the proper cmpxchg8b in order to enable it for
32-bit mode).
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-09-03 03:12:15 +08:00
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config ARCH_USE_CMPXCHG_LOCKREF
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bool
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2014-09-14 02:14:53 +08:00
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config ARCH_HAS_FAST_MULTIPLIER
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bool
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2005-04-17 06:20:36 +08:00
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config CRC_CCITT
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tristate "CRC-CCITT functions"
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help
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This option is provided for the case where no in-kernel-tree
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modules require CRC-CCITT functions, but a module built outside
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the kernel tree does. Such modules that use library CRC-CCITT
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functions require M here.
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2005-08-17 19:17:26 +08:00
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config CRC16
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tristate "CRC16 functions"
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help
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This option is provided for the case where no in-kernel-tree
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modules require CRC16 functions, but a module built outside
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the kernel tree does. Such modules that use library CRC16
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functions require M here.
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2008-06-25 23:22:42 +08:00
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config CRC_T10DIF
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tristate "CRC calculation for the T10 Data Integrity Field"
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2013-09-07 10:56:26 +08:00
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select CRYPTO
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select CRYPTO_CRCT10DIF
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2008-06-25 23:22:42 +08:00
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help
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This option is only needed if a module that's not in the
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kernel tree needs to calculate CRC checks for use with the
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SCSI data integrity subsystem.
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2006-06-12 22:17:04 +08:00
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config CRC_ITU_T
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tristate "CRC ITU-T V.41 functions"
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help
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This option is provided for the case where no in-kernel-tree
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modules require CRC ITU-T V.41 functions, but a module built outside
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the kernel tree does. Such modules that use library CRC ITU-T V.41
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functions require M here.
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2005-04-17 06:20:36 +08:00
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config CRC32
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2012-03-24 06:02:25 +08:00
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tristate "CRC32/CRC32c functions"
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2005-04-17 06:20:36 +08:00
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default y
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2006-12-08 18:36:25 +08:00
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select BITREVERSE
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2005-04-17 06:20:36 +08:00
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help
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This option is provided for the case where no in-kernel-tree
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2012-03-24 06:02:25 +08:00
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modules require CRC32/CRC32c functions, but a module built outside
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the kernel tree does. Such modules that use library CRC32/CRC32c
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functions require M here.
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2005-04-17 06:20:36 +08:00
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2012-03-24 06:02:22 +08:00
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config CRC32_SELFTEST
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bool "CRC32 perform self test on init"
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default n
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depends on CRC32
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help
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This option enables the CRC32 library functions to perform a
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self test on initialization. The self test computes crc32_le
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and crc32_be over byte strings with random alignment and length
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and computes the total elapsed time and number of bytes processed.
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2012-03-24 06:02:26 +08:00
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choice
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prompt "CRC32 implementation"
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depends on CRC32
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default CRC32_SLICEBY8
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2012-03-29 05:42:56 +08:00
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help
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This option allows a kernel builder to override the default choice
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of CRC32 algorithm. Choose the default ("slice by 8") unless you
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know that you need one of the others.
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2012-03-24 06:02:26 +08:00
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config CRC32_SLICEBY8
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bool "Slice by 8 bytes"
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help
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Calculate checksum 8 bytes at a time with a clever slicing algorithm.
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This is the fastest algorithm, but comes with a 8KiB lookup table.
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Most modern processors have enough cache to hold this table without
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thrashing the cache.
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This is the default implementation choice. Choose this one unless
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you have a good reason not to.
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config CRC32_SLICEBY4
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bool "Slice by 4 bytes"
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help
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Calculate checksum 4 bytes at a time with a clever slicing algorithm.
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This is a bit slower than slice by 8, but has a smaller 4KiB lookup
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table.
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Only choose this option if you know what you are doing.
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config CRC32_SARWATE
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bool "Sarwate's Algorithm (one byte at a time)"
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help
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Calculate checksum a byte at a time using Sarwate's algorithm. This
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is not particularly fast, but has a small 256 byte lookup table.
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Only choose this option if you know what you are doing.
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config CRC32_BIT
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bool "Classic Algorithm (one bit at a time)"
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help
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Calculate checksum one bit at a time. This is VERY slow, but has
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no lookup table. This is provided as a debugging option.
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Only choose this option if you are debugging crc32.
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endchoice
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2007-07-17 19:04:03 +08:00
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config CRC7
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tristate "CRC7 functions"
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help
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This option is provided for the case where no in-kernel-tree
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modules require CRC7 functions, but a module built outside
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the kernel tree does. Such modules that use library CRC7
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functions require M here.
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2005-04-17 06:20:36 +08:00
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config LIBCRC32C
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tristate "CRC32c (Castagnoli, et al) Cyclic Redundancy-Check"
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2008-11-13 22:05:13 +08:00
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select CRYPTO
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2008-11-07 15:11:47 +08:00
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select CRYPTO_CRC32C
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2005-04-17 06:20:36 +08:00
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help
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This option is provided for the case where no in-kernel-tree
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modules require CRC32c functions, but a module built outside the
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kernel tree does. Such modules that use library CRC32c functions
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require M here. See Castagnoli93.
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Module will be libcrc32c.
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2011-05-31 17:22:15 +08:00
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config CRC8
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tristate "CRC8 function"
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help
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This option provides CRC8 function. Drivers may select this
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when they need to do cyclic redundancy check according CRC8
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algorithm. Module will be called crc8.
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2006-09-12 15:04:40 +08:00
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config AUDIT_GENERIC
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bool
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depends on AUDIT && !AUDIT_ARCH
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default y
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2014-03-15 13:48:00 +08:00
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config AUDIT_ARCH_COMPAT_GENERIC
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bool
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default n
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config AUDIT_COMPAT_GENERIC
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bool
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depends on AUDIT_GENERIC && AUDIT_ARCH_COMPAT_GENERIC && COMPAT
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default y
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2013-11-11 19:20:37 +08:00
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config RANDOM32_SELFTEST
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bool "PRNG perform self test on init"
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default n
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help
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This option enables the 32 bit PRNG library functions to perform a
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self test on initialization.
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2005-04-17 06:20:36 +08:00
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#
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# compression support is select'ed if needed
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#
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2015-05-08 01:49:14 +08:00
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config 842_COMPRESS
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2016-01-14 06:24:02 +08:00
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select CRC32
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2015-05-08 01:49:14 +08:00
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tristate
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config 842_DECOMPRESS
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2016-01-14 06:24:02 +08:00
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select CRC32
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2015-05-08 01:49:14 +08:00
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tristate
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2005-04-17 06:20:36 +08:00
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config ZLIB_INFLATE
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tristate
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config ZLIB_DEFLATE
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tristate
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2015-10-16 06:28:35 +08:00
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select BITREVERSE
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2005-04-17 06:20:36 +08:00
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2007-07-11 08:22:24 +08:00
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config LZO_COMPRESS
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tristate
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config LZO_DECOMPRESS
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tristate
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2013-07-09 07:01:49 +08:00
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config LZ4_COMPRESS
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tristate
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config LZ4HC_COMPRESS
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tristate
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2013-07-09 07:01:46 +08:00
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config LZ4_DECOMPRESS
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tristate
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2011-01-13 09:01:22 +08:00
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source "lib/xz/Kconfig"
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2009-01-06 05:48:31 +08:00
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#
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# These all provide a common interface (hence the apparent duplication with
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# ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
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#
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config DECOMPRESS_GZIP
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2009-01-07 16:01:43 +08:00
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select ZLIB_INFLATE
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2009-01-06 05:48:31 +08:00
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tristate
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config DECOMPRESS_BZIP2
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tristate
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config DECOMPRESS_LZMA
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tristate
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decompressors: add boot-time XZ support
This implements the API defined in <linux/decompress/generic.h> which is
used for kernel, initramfs, and initrd decompression. This patch together
with the first patch is enough for XZ-compressed initramfs and initrd;
XZ-compressed kernel will need arch-specific changes.
The buffering requirements described in decompress_unxz.c are stricter
than with gzip, so the relevant changes should be done to the
arch-specific code when adding support for XZ-compressed kernel.
Similarly, the heap size in arch-specific pre-boot code may need to be
increased (30 KiB is enough).
The XZ decompressor needs memmove(), memeq() (memcmp() == 0), and
memzero() (memset(ptr, 0, size)), which aren't available in all
arch-specific pre-boot environments. I'm including simple versions in
decompress_unxz.c, but a cleaner solution would naturally be nicer.
Signed-off-by: Lasse Collin <lasse.collin@tukaani.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Alain Knaff <alain@knaff.lu>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Phillip Lougher <phillip@lougher.demon.co.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-01-13 09:01:23 +08:00
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config DECOMPRESS_XZ
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select XZ_DEC
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tristate
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2010-01-09 06:42:46 +08:00
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config DECOMPRESS_LZO
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select LZO_DECOMPRESS
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|
|
|
tristate
|
|
|
|
|
|
2013-07-09 07:01:46 +08:00
|
|
|
config DECOMPRESS_LZ4
|
|
|
|
|
select LZ4_DECOMPRESS
|
|
|
|
|
tristate
|
|
|
|
|
|
2005-06-22 08:15:02 +08:00
|
|
|
#
|
|
|
|
|
# Generic allocator support is selected if needed
|
|
|
|
|
#
|
|
|
|
|
config GENERIC_ALLOCATOR
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2005-06-22 08:15:02 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
|
|
|
|
# reed solomon support is select'ed if needed
|
|
|
|
|
#
|
|
|
|
|
config REED_SOLOMON
|
|
|
|
|
tristate
|
|
|
|
|
|
|
|
|
|
config REED_SOLOMON_ENC8
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
config REED_SOLOMON_DEC8
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
config REED_SOLOMON_ENC16
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
config REED_SOLOMON_DEC16
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2005-04-17 06:20:36 +08:00
|
|
|
|
lib: add shared BCH ECC library
This is a new software BCH encoding/decoding library, similar to the shared
Reed-Solomon library.
Binary BCH (Bose-Chaudhuri-Hocquenghem) codes are widely used to correct
errors in NAND flash devices requiring more than 1-bit ecc correction; they
are generally better suited for NAND flash than RS codes because NAND bit
errors do not occur in bursts. Latest SLC NAND devices typically require at
least 4-bit ecc protection per 512 bytes block.
This library provides software encoding/decoding, but may also be used with
ASIC/SoC hardware BCH engines to perform error correction. It is being
currently used for this purpose on an OMAP3630 board (4bit/8bit HW BCH). It
has also been used to decode raw dumps of NAND devices with on-die BCH ecc
engines (e.g. Micron 4bit ecc SLC devices).
Latest NAND devices (including SLC) can exhibit high error rates (typically
a dozen or more bitflips per hour during stress tests); in order to
minimize the performance impact of error correction, this library
implements recently developed algorithms for fast polynomial root finding
(see bch.c header for details) instead of the traditional exhaustive Chien
root search; a few performance figures are provided below:
Platform: arm926ejs @ 468 MHz, 32 KiB icache, 16 KiB dcache
BCH ecc : 4-bit per 512 bytes
Encoding average throughput: 250 Mbits/s
Error correction time (compared with Chien search):
average worst average (Chien) worst (Chien)
----------------------------------------------------------
1 bit 8.5 µs 11 µs 200 µs 383 µs
2 bit 9.7 µs 12.5 µs 477 µs 728 µs
3 bit 18.1 µs 20.6 µs 758 µs 1010 µs
4 bit 19.5 µs 23 µs 1028 µs 1280 µs
In the above figures, "worst" is meant in terms of error pattern, not in
terms of cache miss / page faults effects (not taken into account here).
The library has been extensively tested on the following platforms: x86,
x86_64, arm926ejs, omap3630, qemu-ppc64, qemu-mips.
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-03-11 18:05:32 +08:00
|
|
|
#
|
|
|
|
|
# BCH support is selected if needed
|
|
|
|
|
#
|
|
|
|
|
config BCH
|
|
|
|
|
tristate
|
|
|
|
|
|
|
|
|
|
config BCH_CONST_PARAMS
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
lib: add shared BCH ECC library
This is a new software BCH encoding/decoding library, similar to the shared
Reed-Solomon library.
Binary BCH (Bose-Chaudhuri-Hocquenghem) codes are widely used to correct
errors in NAND flash devices requiring more than 1-bit ecc correction; they
are generally better suited for NAND flash than RS codes because NAND bit
errors do not occur in bursts. Latest SLC NAND devices typically require at
least 4-bit ecc protection per 512 bytes block.
This library provides software encoding/decoding, but may also be used with
ASIC/SoC hardware BCH engines to perform error correction. It is being
currently used for this purpose on an OMAP3630 board (4bit/8bit HW BCH). It
has also been used to decode raw dumps of NAND devices with on-die BCH ecc
engines (e.g. Micron 4bit ecc SLC devices).
Latest NAND devices (including SLC) can exhibit high error rates (typically
a dozen or more bitflips per hour during stress tests); in order to
minimize the performance impact of error correction, this library
implements recently developed algorithms for fast polynomial root finding
(see bch.c header for details) instead of the traditional exhaustive Chien
root search; a few performance figures are provided below:
Platform: arm926ejs @ 468 MHz, 32 KiB icache, 16 KiB dcache
BCH ecc : 4-bit per 512 bytes
Encoding average throughput: 250 Mbits/s
Error correction time (compared with Chien search):
average worst average (Chien) worst (Chien)
----------------------------------------------------------
1 bit 8.5 µs 11 µs 200 µs 383 µs
2 bit 9.7 µs 12.5 µs 477 µs 728 µs
3 bit 18.1 µs 20.6 µs 758 µs 1010 µs
4 bit 19.5 µs 23 µs 1028 µs 1280 µs
In the above figures, "worst" is meant in terms of error pattern, not in
terms of cache miss / page faults effects (not taken into account here).
The library has been extensively tested on the following platforms: x86,
x86_64, arm926ejs, omap3630, qemu-ppc64, qemu-mips.
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-03-11 18:05:32 +08:00
|
|
|
help
|
|
|
|
|
Drivers may select this option to force specific constant
|
|
|
|
|
values for parameters 'm' (Galois field order) and 't'
|
|
|
|
|
(error correction capability). Those specific values must
|
|
|
|
|
be set by declaring default values for symbols BCH_CONST_M
|
|
|
|
|
and BCH_CONST_T.
|
|
|
|
|
Doing so will enable extra compiler optimizations,
|
|
|
|
|
improving encoding and decoding performance up to 2x for
|
|
|
|
|
usual (m,t) values (typically such that m*t < 200).
|
|
|
|
|
When this option is selected, the BCH library supports
|
|
|
|
|
only a single (m,t) configuration. This is mainly useful
|
|
|
|
|
for NAND flash board drivers requiring known, fixed BCH
|
|
|
|
|
parameters.
|
|
|
|
|
|
|
|
|
|
config BCH_CONST_M
|
|
|
|
|
int
|
|
|
|
|
range 5 15
|
|
|
|
|
help
|
|
|
|
|
Constant value for Galois field order 'm'. If 'k' is the
|
|
|
|
|
number of data bits to protect, 'm' should be chosen such
|
|
|
|
|
that (k + m*t) <= 2**m - 1.
|
|
|
|
|
Drivers should declare a default value for this symbol if
|
|
|
|
|
they select option BCH_CONST_PARAMS.
|
|
|
|
|
|
|
|
|
|
config BCH_CONST_T
|
|
|
|
|
int
|
|
|
|
|
help
|
|
|
|
|
Constant value for error correction capability in bits 't'.
|
|
|
|
|
Drivers should declare a default value for this symbol if
|
|
|
|
|
they select option BCH_CONST_PARAMS.
|
|
|
|
|
|
2005-06-25 08:39:03 +08:00
|
|
|
#
|
|
|
|
|
# Textsearch support is select'ed if needed
|
|
|
|
|
#
|
2005-06-24 11:49:30 +08:00
|
|
|
config TEXTSEARCH
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2005-04-17 06:20:36 +08:00
|
|
|
|
[LIB]: Knuth-Morris-Pratt textsearch algorithm
Implements a linear-time string-matching algorithm due to Knuth,
Morris, and Pratt [1]. Their algorithm avoids the explicit
computation of the transition function DELTA altogether. Its
matching time is O(n), for n being length(text), using just an
auxiliary function PI[1..m], for m being length(pattern),
precomputed from the pattern in time O(m). The array PI allows
the transition function DELTA to be computed efficiently
"on the fly" as needed. Roughly speaking, for any state
"q" = 0,1,...,m and any character "a" in SIGMA, the value
PI["q"] contains the information that is independent of "a" and
is needed to compute DELTA("q", "a") [2]. Since the array PI
has only m entries, whereas DELTA has O(m|SIGMA|) entries, we
save a factor of |SIGMA| in the preprocessing time by computing
PI rather than DELTA.
[1] Cormen, Leiserson, Rivest, Stein
Introdcution to Algorithms, 2nd Edition, MIT Press
[2] See finite automation theory
Signed-off-by: Thomas Graf <tgraf@suug.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-24 11:58:37 +08:00
|
|
|
config TEXTSEARCH_KMP
|
2005-06-25 08:39:03 +08:00
|
|
|
tristate
|
[LIB]: Knuth-Morris-Pratt textsearch algorithm
Implements a linear-time string-matching algorithm due to Knuth,
Morris, and Pratt [1]. Their algorithm avoids the explicit
computation of the transition function DELTA altogether. Its
matching time is O(n), for n being length(text), using just an
auxiliary function PI[1..m], for m being length(pattern),
precomputed from the pattern in time O(m). The array PI allows
the transition function DELTA to be computed efficiently
"on the fly" as needed. Roughly speaking, for any state
"q" = 0,1,...,m and any character "a" in SIGMA, the value
PI["q"] contains the information that is independent of "a" and
is needed to compute DELTA("q", "a") [2]. Since the array PI
has only m entries, whereas DELTA has O(m|SIGMA|) entries, we
save a factor of |SIGMA| in the preprocessing time by computing
PI rather than DELTA.
[1] Cormen, Leiserson, Rivest, Stein
Introdcution to Algorithms, 2nd Edition, MIT Press
[2] See finite automation theory
Signed-off-by: Thomas Graf <tgraf@suug.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-24 11:58:37 +08:00
|
|
|
|
2005-08-26 07:12:22 +08:00
|
|
|
config TEXTSEARCH_BM
|
2005-08-26 07:23:11 +08:00
|
|
|
tristate
|
2005-08-26 07:12:22 +08:00
|
|
|
|
2005-06-24 11:59:16 +08:00
|
|
|
config TEXTSEARCH_FSM
|
2005-06-25 08:39:03 +08:00
|
|
|
tristate
|
2005-06-24 11:59:16 +08:00
|
|
|
|
2009-11-21 03:13:39 +08:00
|
|
|
config BTREE
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2009-11-21 03:13:39 +08:00
|
|
|
|
2014-03-17 20:21:54 +08:00
|
|
|
config INTERVAL_TREE
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2014-03-17 20:21:54 +08:00
|
|
|
help
|
|
|
|
|
Simple, embeddable, interval-tree. Can find the start of an
|
|
|
|
|
overlapping range in log(n) time and then iterate over all
|
|
|
|
|
overlapping nodes. The algorithm is implemented as an
|
|
|
|
|
augmented rbtree.
|
|
|
|
|
|
|
|
|
|
See:
|
|
|
|
|
|
|
|
|
|
Documentation/rbtree.txt
|
|
|
|
|
|
|
|
|
|
for more information.
|
|
|
|
|
|
2016-05-21 08:01:54 +08:00
|
|
|
config RADIX_TREE_MULTIORDER
|
|
|
|
|
bool
|
|
|
|
|
|
Add a generic associative array implementation.
Add a generic associative array implementation that can be used as the
container for keyrings, thereby massively increasing the capacity available
whilst also speeding up searching in keyrings that contain a lot of keys.
This may also be useful in FS-Cache for tracking cookies.
Documentation is added into Documentation/associative_array.txt
Some of the properties of the implementation are:
(1) Objects are opaque pointers. The implementation does not care where they
point (if anywhere) or what they point to (if anything).
[!] NOTE: Pointers to objects _must_ be zero in the two least significant
bits.
(2) Objects do not need to contain linkage blocks for use by the array. This
permits an object to be located in multiple arrays simultaneously.
Rather, the array is made up of metadata blocks that point to objects.
(3) Objects are labelled as being one of two types (the type is a bool value).
This information is stored in the array, but has no consequence to the
array itself or its algorithms.
(4) Objects require index keys to locate them within the array.
(5) Index keys must be unique. Inserting an object with the same key as one
already in the array will replace the old object.
(6) Index keys can be of any length and can be of different lengths.
(7) Index keys should encode the length early on, before any variation due to
length is seen.
(8) Index keys can include a hash to scatter objects throughout the array.
(9) The array can iterated over. The objects will not necessarily come out in
key order.
(10) The array can be iterated whilst it is being modified, provided the RCU
readlock is being held by the iterator. Note, however, under these
circumstances, some objects may be seen more than once. If this is a
problem, the iterator should lock against modification. Objects will not
be missed, however, unless deleted.
(11) Objects in the array can be looked up by means of their index key.
(12) Objects can be looked up whilst the array is being modified, provided the
RCU readlock is being held by the thread doing the look up.
The implementation uses a tree of 16-pointer nodes internally that are indexed
on each level by nibbles from the index key. To improve memory efficiency,
shortcuts can be emplaced to skip over what would otherwise be a series of
single-occupancy nodes. Further, nodes pack leaf object pointers into spare
space in the node rather than making an extra branch until as such time an
object needs to be added to a full node.
Signed-off-by: David Howells <dhowells@redhat.com>
2013-09-24 17:35:17 +08:00
|
|
|
config ASSOCIATIVE_ARRAY
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Generic associative array. Can be searched and iterated over whilst
|
|
|
|
|
it is being modified. It is also reasonably quick to search and
|
|
|
|
|
modify. The algorithms are non-recursive, and the trees are highly
|
|
|
|
|
capacious.
|
|
|
|
|
|
|
|
|
|
See:
|
|
|
|
|
|
|
|
|
|
Documentation/assoc_array.txt
|
|
|
|
|
|
|
|
|
|
for more information.
|
|
|
|
|
|
2007-02-11 23:41:31 +08:00
|
|
|
config HAS_IOMEM
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2007-02-11 23:41:31 +08:00
|
|
|
depends on !NO_IOMEM
|
2012-02-07 08:22:46 +08:00
|
|
|
select GENERIC_IO
|
2007-02-11 23:41:31 +08:00
|
|
|
default y
|
|
|
|
|
|
2014-04-08 06:39:19 +08:00
|
|
|
config HAS_IOPORT_MAP
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2014-04-08 06:39:19 +08:00
|
|
|
depends on HAS_IOMEM && !NO_IOPORT_MAP
|
2006-12-13 16:35:00 +08:00
|
|
|
default y
|
|
|
|
|
|
2007-05-07 05:49:09 +08:00
|
|
|
config HAS_DMA
|
2014-12-21 04:41:11 +08:00
|
|
|
bool
|
2007-05-07 05:49:09 +08:00
|
|
|
depends on !NO_DMA
|
|
|
|
|
default y
|
|
|
|
|
|
2007-08-23 05:01:36 +08:00
|
|
|
config CHECK_SIGNATURE
|
|
|
|
|
bool
|
|
|
|
|
|
2008-12-13 18:50:27 +08:00
|
|
|
config CPUMASK_OFFSTACK
|
|
|
|
|
bool "Force CPU masks off stack" if DEBUG_PER_CPU_MAPS
|
|
|
|
|
help
|
|
|
|
|
Use dynamic allocation for cpumask_var_t, instead of putting
|
|
|
|
|
them on the stack. This is a bit more expensive, but avoids
|
|
|
|
|
stack overflow.
|
|
|
|
|
|
2011-01-19 19:03:25 +08:00
|
|
|
config CPU_RMAP
|
|
|
|
|
bool
|
|
|
|
|
depends on SMP
|
|
|
|
|
|
dql: Dynamic queue limits
Implementation of dynamic queue limits (dql). This is a libary which
allows a queue limit to be dynamically managed. The goal of dql is
to set the queue limit, number of objects to the queue, to be minimized
without allowing the queue to be starved.
dql would be used with a queue which has these properties:
1) Objects are queued up to some limit which can be expressed as a
count of objects.
2) Periodically a completion process executes which retires consumed
objects.
3) Starvation occurs when limit has been reached, all queued data has
actually been consumed but completion processing has not yet run,
so queuing new data is blocked.
4) Minimizing the amount of queued data is desirable.
A canonical example of such a queue would be a NIC HW transmit queue.
The queue limit is dynamic, it will increase or decrease over time
depending on the workload. The queue limit is recalculated each time
completion processing is done. Increases occur when the queue is
starved and can exponentially increase over successive intervals.
Decreases occur when more data is being maintained in the queue than
needed to prevent starvation. The number of extra objects, or "slack",
is measured over successive intervals, and to avoid hysteresis the
limit is only reduced by the miminum slack seen over a configurable
time period.
dql API provides routines to manage the queue:
- dql_init is called to intialize the dql structure
- dql_reset is called to reset dynamic values
- dql_queued called when objects are being enqueued
- dql_avail returns availability in the queue
- dql_completed is called when objects have be consumed in the queue
Configuration consists of:
- max_limit, maximum limit
- min_limit, minimum limit
- slack_hold_time, time to measure instances of slack before reducing
queue limit
Signed-off-by: Tom Herbert <therbert@google.com>
Acked-by: Eric Dumazet <eric.dumazet@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-11-29 00:32:35 +08:00
|
|
|
config DQL
|
|
|
|
|
bool
|
|
|
|
|
|
2014-08-07 07:09:23 +08:00
|
|
|
config GLOB
|
|
|
|
|
bool
|
|
|
|
|
# This actually supports modular compilation, but the module overhead
|
|
|
|
|
# is ridiculous for the amount of code involved. Until an out-of-tree
|
|
|
|
|
# driver asks for it, we'll just link it directly it into the kernel
|
|
|
|
|
# when required. Since we're ignoring out-of-tree users, there's also
|
|
|
|
|
# no need bother prompting for a manual decision:
|
|
|
|
|
# prompt "glob_match() function"
|
|
|
|
|
help
|
|
|
|
|
This option provides a glob_match function for performing
|
|
|
|
|
simple text pattern matching. It originated in the ATA code
|
|
|
|
|
to blacklist particular drive models, but other device drivers
|
|
|
|
|
may need similar functionality.
|
|
|
|
|
|
|
|
|
|
All drivers in the Linux kernel tree that require this function
|
|
|
|
|
should automatically select this option. Say N unless you
|
|
|
|
|
are compiling an out-of tree driver which tells you that it
|
|
|
|
|
depends on this.
|
|
|
|
|
|
2014-08-07 07:09:25 +08:00
|
|
|
config GLOB_SELFTEST
|
|
|
|
|
bool "glob self-test on init"
|
|
|
|
|
default n
|
|
|
|
|
depends on GLOB
|
|
|
|
|
help
|
|
|
|
|
This option enables a simple self-test of the glob_match
|
|
|
|
|
function on startup. It is primarily useful for people
|
|
|
|
|
working on the code to ensure they haven't introduced any
|
|
|
|
|
regressions.
|
|
|
|
|
|
|
|
|
|
It only adds a little bit of code and slows kernel boot (or
|
|
|
|
|
module load) by a small amount, so you're welcome to play with
|
|
|
|
|
it, but you probably don't need it.
|
|
|
|
|
|
2009-03-04 14:53:30 +08:00
|
|
|
#
|
|
|
|
|
# Netlink attribute parsing support is select'ed if needed
|
|
|
|
|
#
|
|
|
|
|
config NLATTR
|
|
|
|
|
bool
|
|
|
|
|
|
2009-06-13 05:10:05 +08:00
|
|
|
#
|
|
|
|
|
# Generic 64-bit atomic support is selected if needed
|
|
|
|
|
#
|
|
|
|
|
config GENERIC_ATOMIC64
|
|
|
|
|
bool
|
|
|
|
|
|
2012-07-31 05:41:09 +08:00
|
|
|
config ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
|
|
|
|
|
def_bool y if GENERIC_ATOMIC64
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2009-09-26 07:07:19 +08:00
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config LRU_CACHE
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tristate
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2012-02-02 06:17:54 +08:00
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config CLZ_TAB
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bool
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2011-05-31 17:22:16 +08:00
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config CORDIC
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2011-07-29 20:59:51 +08:00
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tristate "CORDIC algorithm"
|
2011-05-31 17:22:16 +08:00
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help
|
2011-07-29 21:36:04 +08:00
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This option provides an implementation of the CORDIC algorithm;
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calculations are in fixed point. Module will be called cordic.
|
2011-05-31 17:22:16 +08:00
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2012-04-27 20:24:03 +08:00
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config DDR
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bool "JEDEC DDR data"
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help
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Data from JEDEC specs for DDR SDRAM memories,
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|
particularly the AC timing parameters and addressing
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|
information. This data is useful for drivers handling
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DDR SDRAM controllers.
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2015-11-10 21:56:14 +08:00
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config IRQ_POLL
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bool "IRQ polling library"
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|
help
|
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|
|
Helper library to poll interrupt mitigation using polling.
|
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|
2011-08-31 19:05:16 +08:00
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|
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config MPILIB
|
2012-01-17 23:12:06 +08:00
|
|
|
tristate
|
2012-02-02 06:17:54 +08:00
|
|
|
select CLZ_TAB
|
2011-08-31 19:05:16 +08:00
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|
help
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|
Multiprecision maths library from GnuPG.
|
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|
It is used to implement RSA digital signature verification,
|
|
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|
|
which is used by IMA/EVM digital signature extension.
|
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|
2012-01-17 23:12:03 +08:00
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config SIGNATURE
|
2012-01-17 23:12:06 +08:00
|
|
|
tristate
|
2014-07-11 23:59:45 +08:00
|
|
|
depends on KEYS
|
|
|
|
|
select CRYPTO
|
2012-01-17 23:12:04 +08:00
|
|
|
select CRYPTO_SHA1
|
2011-10-14 20:25:16 +08:00
|
|
|
select MPILIB
|
|
|
|
|
help
|
|
|
|
|
Digital signature verification. Currently only RSA is supported.
|
|
|
|
|
Implementation is done using GnuPG MPI library
|
|
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|
|
2012-07-06 00:12:38 +08:00
|
|
|
#
|
|
|
|
|
# libfdt files, only selected if needed.
|
|
|
|
|
#
|
|
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|
|
config LIBFDT
|
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|
bool
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|
|
2012-09-22 06:30:46 +08:00
|
|
|
config OID_REGISTRY
|
|
|
|
|
tristate
|
|
|
|
|
help
|
|
|
|
|
Enable fast lookup object identifier registry.
|
|
|
|
|
|
2013-04-16 04:09:45 +08:00
|
|
|
config UCS2_STRING
|
|
|
|
|
tristate
|
|
|
|
|
|
2013-06-09 17:46:43 +08:00
|
|
|
source "lib/fonts/Kconfig"
|
|
|
|
|
|
lib: scatterlist: add sg splitting function
Sometimes a scatter-gather has to be split into several chunks, or sub
scatter lists. This happens for example if a scatter list will be
handled by multiple DMA channels, each one filling a part of it.
A concrete example comes with the media V4L2 API, where the scatter list
is allocated from userspace to hold an image, regardless of the
knowledge of how many DMAs will fill it :
- in a simple RGB565 case, one DMA will pump data from the camera ISP
to memory
- in the trickier YUV422 case, 3 DMAs will pump data from the camera
ISP pipes, one for pipe Y, one for pipe U and one for pipe V
For these cases, it is necessary to split the original scatter list into
multiple scatter lists, which is the purpose of this patch.
The guarantees that are required for this patch are :
- the intersection of spans of any couple of resulting scatter lists is
empty.
- the union of spans of all resulting scatter lists is a subrange of
the span of the original scatter list.
- streaming DMA API operations (mapping, unmapping) should not happen
both on both the resulting and the original scatter list. It's either
the first or the later ones.
- the caller is reponsible to call kfree() on the resulting
scatterlists.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Jens Axboe <axboe@fb.com>
2015-08-08 16:44:10 +08:00
|
|
|
config SG_SPLIT
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
2015-09-04 18:45:05 +08:00
|
|
|
Provides a helper to split scatterlists into chunks, each chunk being
|
|
|
|
|
a scatterlist. This should be selected by a driver or an API which
|
|
|
|
|
whishes to split a scatterlist amongst multiple DMA channels.
|
lib: scatterlist: add sg splitting function
Sometimes a scatter-gather has to be split into several chunks, or sub
scatter lists. This happens for example if a scatter list will be
handled by multiple DMA channels, each one filling a part of it.
A concrete example comes with the media V4L2 API, where the scatter list
is allocated from userspace to hold an image, regardless of the
knowledge of how many DMAs will fill it :
- in a simple RGB565 case, one DMA will pump data from the camera ISP
to memory
- in the trickier YUV422 case, 3 DMAs will pump data from the camera
ISP pipes, one for pipe Y, one for pipe U and one for pipe V
For these cases, it is necessary to split the original scatter list into
multiple scatter lists, which is the purpose of this patch.
The guarantees that are required for this patch are :
- the intersection of spans of any couple of resulting scatter lists is
empty.
- the union of spans of all resulting scatter lists is a subrange of
the span of the original scatter list.
- streaming DMA API operations (mapping, unmapping) should not happen
both on both the resulting and the original scatter list. It's either
the first or the later ones.
- the caller is reponsible to call kfree() on the resulting
scatterlists.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Jens Axboe <axboe@fb.com>
2015-08-08 16:44:10 +08:00
|
|
|
|
2016-04-05 05:48:11 +08:00
|
|
|
config SG_POOL
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Provides a helper to allocate chained scatterlists. This should be
|
|
|
|
|
selected by a driver or an API which whishes to allocate chained
|
|
|
|
|
scatterlist.
|
|
|
|
|
|
2014-08-09 05:23:25 +08:00
|
|
|
#
|
|
|
|
|
# sg chaining option
|
|
|
|
|
#
|
|
|
|
|
|
|
|
|
|
config ARCH_HAS_SG_CHAIN
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2015-06-25 15:08:39 +08:00
|
|
|
config ARCH_HAS_PMEM_API
|
|
|
|
|
bool
|
|
|
|
|
|
nd_blk: change aperture mapping from WC to WB
This should result in a pretty sizeable performance gain for reads. For
rough comparison I did some simple read testing using PMEM to compare
reads of write combining (WC) mappings vs write-back (WB). This was
done on a random lab machine.
PMEM reads from a write combining mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=100000
100000+0 records in
100000+0 records out
409600000 bytes (410 MB) copied, 9.2855 s, 44.1 MB/s
PMEM reads from a write-back mapping:
# dd of=/dev/null if=/dev/pmem0 bs=4096 count=1000000
1000000+0 records in
1000000+0 records out
4096000000 bytes (4.1 GB) copied, 3.44034 s, 1.2 GB/s
To be able to safely support a write-back aperture I needed to add
support for the "read flush" _DSM flag, as outlined in the DSM spec:
http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
This flag tells the ND BLK driver that it needs to flush the cache lines
associated with the aperture after the aperture is moved but before any
new data is read. This ensures that any stale cache lines from the
previous contents of the aperture will be discarded from the processor
cache, and the new data will be read properly from the DIMM. We know
that the cache lines are clean and will be discarded without any
writeback because either a) the previous aperture operation was a read,
and we never modified the contents of the aperture, or b) the previous
aperture operation was a write and we must have written back the dirtied
contents of the aperture to the DIMM before the I/O was completed.
In order to add support for the "read flush" flag I needed to add a
generic routine to invalidate cache lines, mmio_flush_range(). This is
protected by the ARCH_HAS_MMIO_FLUSH Kconfig variable, and is currently
only supported on x86.
Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2015-08-28 03:14:20 +08:00
|
|
|
config ARCH_HAS_MMIO_FLUSH
|
|
|
|
|
bool
|
|
|
|
|
|
2016-03-26 05:22:08 +08:00
|
|
|
config STACKDEPOT
|
|
|
|
|
bool
|
|
|
|
|
select STACKTRACE
|
|
|
|
|
|
2005-06-24 11:49:30 +08:00
|
|
|
endmenu
|