forked from luck/tmp_suning_uos_patched
137 lines
7.4 KiB
C
137 lines
7.4 KiB
C
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/* $Id: act2000_isa.h,v 1.4.6.1 2001/09/23 22:24:32 kai Exp $
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*
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* ISDN lowlevel-module for the IBM ISDN-S0 Active 2000 (ISA-Version).
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*
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* Author Fritz Elfert
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* Copyright by Fritz Elfert <fritz@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* Thanks to Friedemann Baitinger and IBM Germany
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*
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*/
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#ifndef act2000_isa_h
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#define act2000_isa_h
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#define ISA_POLL_LOOP 40 /* Try to read-write before give up */
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typedef enum {
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INT_NO_CHANGE = 0, /* Do not change the Mask */
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INT_ON = 1, /* Set to Enable */
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INT_OFF = 2, /* Set to Disable */
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} ISA_INT_T;
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/**************************************************************************/
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/* Configuration Register COR (RW) */
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/**************************************************************************/
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/* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 */
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/* Soft Res| IRQM | IRQ Select | N/A | WAIT |Proc err */
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/**************************************************************************/
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#define ISA_COR 0 /* Offset for ISA config register */
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#define ISA_COR_PERR 0x01 /* Processor Error Enabled */
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#define ISA_COR_WS 0x02 /* Insert Wait State if 1 */
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#define ISA_COR_IRQOFF 0x38 /* No Interrupt */
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#define ISA_COR_IRQ07 0x30 /* IRQ 7 Enable */
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#define ISA_COR_IRQ05 0x28 /* IRQ 5 Enable */
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#define ISA_COR_IRQ03 0x20 /* IRQ 3 Enable */
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#define ISA_COR_IRQ10 0x18 /* IRQ 10 Enable */
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#define ISA_COR_IRQ11 0x10 /* IRQ 11 Enable */
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#define ISA_COR_IRQ12 0x08 /* IRQ 12 Enable */
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#define ISA_COR_IRQ15 0x00 /* IRQ 15 Enable */
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#define ISA_COR_IRQPULSE 0x40 /* 0 = Level 1 = Pulse Interrupt */
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#define ISA_COR_RESET 0x80 /* Soft Reset for Transputer */
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/**************************************************************************/
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/* Interrupt Source Register ISR (RO) */
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/**************************************************************************/
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/* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 */
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/* N/A | N/A | N/A |Err sig |Ser ID |IN Intr |Out Intr| Error */
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/**************************************************************************/
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#define ISA_ISR 1 /* Offset for Interrupt Register */
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#define ISA_ISR_ERR 0x01 /* Error Interrupt */
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#define ISA_ISR_OUT 0x02 /* Output Interrupt */
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#define ISA_ISR_INP 0x04 /* Input Interrupt */
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#define ISA_ISR_SERIAL 0x08 /* Read out Serial ID after Reset */
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#define ISA_ISR_ERRSIG 0x10 /* Error Signal Input */
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#define ISA_ISR_ERR_MASK 0xfe /* Mask Error Interrupt */
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#define ISA_ISR_OUT_MASK 0xfd /* Mask Output Interrupt */
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#define ISA_ISR_INP_MASK 0xfb /* Mask Input Interrupt */
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/* Signature delivered after Reset at ISA_ISR_SERIAL (LSB first) */
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#define ISA_SER_ID 0x0201 /* ID for ISA Card */
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/**************************************************************************/
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/* EEPROM Register EPR (RW) */
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/**************************************************************************/
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/* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 */
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/* N/A | N/A | N/A |ROM Hold| ROM CS |ROM CLK | ROM IN |ROM Out */
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/**************************************************************************/
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#define ISA_EPR 2 /* Offset for this Register */
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#define ISA_EPR_OUT 0x01 /* Rome Register Out (RO) */
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#define ISA_EPR_IN 0x02 /* Rom Register In (WR) */
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#define ISA_EPR_CLK 0x04 /* Rom Clock (WR) */
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#define ISA_EPR_CS 0x08 /* Rom Cip Select (WR) */
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#define ISA_EPR_HOLD 0x10 /* Rom Hold Signal (WR) */
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/**************************************************************************/
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/* EEPROM enable Register EER (unused) */
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/**************************************************************************/
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#define ISA_EER 3 /* Offset for this Register */
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/**************************************************************************/
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/* SLC Data Input SDI (RO) */
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/**************************************************************************/
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#define ISA_SDI 4 /* Offset for this Register */
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/**************************************************************************/
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/* SLC Data Output SDO (WO) */
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/**************************************************************************/
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#define ISA_SDO 5 /* Offset for this Register */
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/**************************************************************************/
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/* IMS C011 Mode 2 Input Status Register for INMOS CPU SIS (RW) */
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/**************************************************************************/
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/* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 */
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/* N/A | N/A | N/A | N/A | N/A | N/A |Int Ena |Data Pre */
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/**************************************************************************/
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#define ISA_SIS 6 /* Offset for this Register */
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#define ISA_SIS_READY 0x01 /* If 1 : data is available */
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#define ISA_SIS_INT 0x02 /* Enable Interrupt for READ */
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/**************************************************************************/
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/* IMS C011 Mode 2 Output Status Register from INMOS CPU SOS (RW) */
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/**************************************************************************/
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/* 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 */
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/* N/A | N/A | N/A | N/A | N/A | N/A |Int Ena |Out Rdy */
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/**************************************************************************/
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#define ISA_SOS 7 /* Offset for this Register */
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#define ISA_SOS_READY 0x01 /* If 1 : we can write Data */
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#define ISA_SOS_INT 0x02 /* Enable Interrupt for WRITE */
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#define ISA_REGION 8 /* Number of Registers */
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/* Macros for accessing ports */
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#define ISA_PORT_COR (card->port+ISA_COR)
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#define ISA_PORT_ISR (card->port+ISA_ISR)
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#define ISA_PORT_EPR (card->port+ISA_EPR)
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#define ISA_PORT_EER (card->port+ISA_EER)
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#define ISA_PORT_SDI (card->port+ISA_SDI)
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#define ISA_PORT_SDO (card->port+ISA_SDO)
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#define ISA_PORT_SIS (card->port+ISA_SIS)
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#define ISA_PORT_SOS (card->port+ISA_SOS)
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/* Prototypes */
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extern int act2000_isa_detect(unsigned short portbase);
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extern int act2000_isa_config_irq(act2000_card * card, short irq);
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extern int act2000_isa_config_port(act2000_card * card, unsigned short portbase);
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extern int act2000_isa_download(act2000_card * card, act2000_ddef __user * cb);
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extern void act2000_isa_release(act2000_card * card);
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extern void act2000_isa_receive(act2000_card *card);
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extern void act2000_isa_send(act2000_card *card);
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#endif /* act2000_isa_h */
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