2013-01-18 17:42:18 +08:00
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Jan 1011
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* -sched_clock( ) no longer jiffies based. Uses the same clocksource
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* as gtod
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*
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* Rajeshwarr/Vineetg: Mar 2008
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* -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
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* for arch independent gettimeofday()
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* -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
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*
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* Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
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*/
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/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
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* Each can programmed to go from @count to @limit and optionally
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* interrupt when that happens.
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* A write to Control Register clears the Interrupt
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*
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* We've designated TIMER0 for events (clockevents)
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* while TIMER1 for free running (clocksource)
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*
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* Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
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*/
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/profile.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/irq.h>
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#include <asm/arcregs.h>
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#include <asm/clk.h>
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2013-01-18 17:42:26 +08:00
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#include <asm/mach_desc.h>
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2013-01-18 17:42:18 +08:00
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2013-05-14 15:58:17 +08:00
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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2013-01-18 17:42:18 +08:00
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#define ARC_TIMER_MAX 0xFFFFFFFF
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/********** Clock Source Device *********/
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#ifdef CONFIG_ARC_HAS_RTSC
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2013-06-25 03:30:15 +08:00
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int arc_counter_setup(void)
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2013-01-18 17:42:18 +08:00
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{
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2013-09-09 18:34:15 +08:00
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/*
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* For SMP this needs to be 0. However Kconfig glue doesn't
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* enable this option for SMP configs
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*/
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2013-01-18 17:42:18 +08:00
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return 1;
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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{
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unsigned long flags;
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union {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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struct { u32 high, low; };
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#else
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struct { u32 low, high; };
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#endif
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cycle_t full;
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} stamp;
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flags = arch_local_irq_save();
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__asm__ __volatile(
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" .extCoreRegister tsch, 58, r, cannot_shortcut \n"
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" rtsc %0, 0 \n"
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2013-02-06 17:39:13 +08:00
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" mov %1, 0 \n"
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2013-01-18 17:42:18 +08:00
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: "=r" (stamp.low), "=r" (stamp.high));
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arch_local_irq_restore(flags);
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return stamp.full;
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}
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static struct clocksource arc_counter = {
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.name = "ARC RTSC",
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.rating = 300,
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.read = arc_counter_read,
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2013-02-06 17:39:13 +08:00
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.mask = CLOCKSOURCE_MASK(32),
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2013-01-18 17:42:18 +08:00
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#else /* !CONFIG_ARC_HAS_RTSC */
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static bool is_usable_as_clocksource(void)
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{
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#ifdef CONFIG_SMP
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return 0;
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#else
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return 1;
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#endif
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}
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/*
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* set 32bit TIMER1 to keep counting monotonically and wraparound
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*/
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2013-06-25 03:30:15 +08:00
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int arc_counter_setup(void)
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2013-01-18 17:42:18 +08:00
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{
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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return is_usable_as_clocksource();
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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{
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return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
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}
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static struct clocksource arc_counter = {
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.name = "ARC Timer1",
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.rating = 300,
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.read = arc_counter_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#endif
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/********** Clock Event Device *********/
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/*
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* Arm the timer to interrupt after @limit cycles
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* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
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*/
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static void arc_timer_event_setup(unsigned int limit)
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{
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write_aux_reg(ARC_REG_TIMER0_LIMIT, limit);
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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}
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/*
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* Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic)
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* -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted)
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* -Rearming is done by setting the IE bit
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*
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* Small optimisation: Normal code would have been
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* if (irq_reenable)
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* CTRL_REG = (IE | NH);
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* else
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* CTRL_REG = NH;
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* However since IE is BIT0 we can fold the branch
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*/
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static void arc_timer_event_ack(unsigned int irq_reenable)
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{
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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}
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static int arc_clkevent_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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arc_timer_event_setup(delta);
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return 0;
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}
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static void arc_clkevent_set_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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arc_timer_event_setup(arc_get_core_freq() / HZ);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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default:
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break;
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}
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return;
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}
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static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
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.name = "ARC Timer0",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.mode = CLOCK_EVT_MODE_UNUSED,
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.rating = 300,
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.irq = TIMER0_IRQ, /* hardwired, no need for resources */
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.set_next_event = arc_clkevent_set_next_event,
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.set_mode = arc_clkevent_set_mode,
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};
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static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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{
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arc: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of them is
address calculation via the form &__get_cpu_var(x). This calculates the address for
the instance of the percpu variable of the current processor based on an offset.
Other use cases are for storing and retrieving data from the current processors percpu area.
__get_cpu_var() can be used as an lvalue when writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store and retrieve operations
could use a segment prefix (or global register on other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a percpu area and use
optimized assembly code to read and write per cpu variables.
This patch converts __get_cpu_var into either an explicit address calculation using this_cpu_ptr()
or into a use of this_cpu operations that use the offset. Thereby address calcualtions are avoided
and less registers are used when code is generated.
At the end of the patchset all uses of __get_cpu_var have been removed so the macro is removed too.
The patchset includes passes over all arches as well. Once these operations are used throughout then
specialized macros can be defined in non -x86 arches as well in order to optimize per cpu access by
f.e. using a global register that may be set to the per cpu base.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu variable.
DEFINE_PER_CPU(int, u);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(this_cpu_ptr(&x), y, sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
this_cpu_inc(y)
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Christoph Lameter <cl@linux.com>
2013-08-29 03:48:15 +08:00
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struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device);
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2013-01-18 17:42:18 +08:00
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arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC);
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clk->event_handler(clk);
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return IRQ_HANDLED;
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}
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static struct irqaction arc_timer_irq = {
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.name = "Timer0 (clock-evt-dev)",
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.flags = IRQF_TIMER | IRQF_PERCPU,
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.handler = timer_irq_handler,
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};
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/*
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* Setup the local event timer for @cpu
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* N.B. weak so that some exotic ARC SoCs can completely override it
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*/
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2013-10-31 16:23:54 +08:00
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void __weak arc_local_timer_setup(unsigned int cpu)
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2013-01-18 17:42:18 +08:00
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{
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struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
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clk->cpumask = cpumask_of(cpu);
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2013-09-25 05:05:37 +08:00
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clockevents_config_and_register(clk, arc_get_core_freq(),
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0, ARC_TIMER_MAX);
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2013-01-18 17:42:18 +08:00
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/*
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* setup the per-cpu timer IRQ handler - for all cpus
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* For non boot CPU explicitly unmask at intc
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* setup_irq() -> .. -> irq_startup() already does this on boot-cpu
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*/
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if (!cpu)
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setup_irq(TIMER0_IRQ, &arc_timer_irq);
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else
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arch_unmask_irq(TIMER0_IRQ);
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}
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/*
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* Called from start_kernel() - boot CPU only
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*
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* -Sets up h/w timers as applicable on boot cpu
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* -Also sets up any global state needed for timer subsystem:
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* - for "counting" timer, registers a clocksource, usable across CPUs
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* (provided that underlying counter h/w is synchronized across cores)
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* - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
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*/
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void __init time_init(void)
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{
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/*
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* sets up the timekeeping free-flowing counter which also returns
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* whether the counter is usable as clocksource
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*/
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if (arc_counter_setup())
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/*
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* CLK upto 4.29 GHz can be safely represented in 32 bits
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* because Max 32 bit number is 4,294,967,295
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*/
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clocksource_register_hz(&arc_counter, arc_get_core_freq());
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/* sets up the periodic event timer */
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arc_local_timer_setup(smp_processor_id());
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2013-01-18 17:42:26 +08:00
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if (machine_desc->init_time)
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machine_desc->init_time();
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2013-01-18 17:42:18 +08:00
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}
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