2005-04-17 06:20:36 +08:00
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/*
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* linux/arch/alpha/kernel/sys_wildfire.c
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*
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* Wildfire support.
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_wildfire.h>
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#include <asm/hwrpb.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)];
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DEFINE_SPINLOCK(wildfire_irq_lock);
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static int doing_init_irq_hw = 0;
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static void
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wildfire_update_irq_hw(unsigned int irq)
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{
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int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1);
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int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1);
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wildfire_pca *pca;
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volatile unsigned long * enable0;
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if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
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if (!doing_init_irq_hw) {
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printk(KERN_ERR "wildfire_update_irq_hw:"
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" got irq %d for non-existent PCA %d"
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" on QBB %d.\n",
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irq, pcano, qbbno);
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}
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return;
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}
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pca = WILDFIRE_pca(qbbno, pcano);
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enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */
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*enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano];
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mb();
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*enable0;
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}
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static void __init
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wildfire_init_irq_hw(void)
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{
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#if 0
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register wildfire_pca * pca = WILDFIRE_pca(0, 0);
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volatile unsigned long * enable0, * enable1, * enable2, *enable3;
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volatile unsigned long * target0, * target1, * target2, *target3;
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enable0 = (unsigned long *) &pca->pca_int[0].enable;
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enable1 = (unsigned long *) &pca->pca_int[1].enable;
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enable2 = (unsigned long *) &pca->pca_int[2].enable;
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enable3 = (unsigned long *) &pca->pca_int[3].enable;
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target0 = (unsigned long *) &pca->pca_int[0].target;
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target1 = (unsigned long *) &pca->pca_int[1].target;
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target2 = (unsigned long *) &pca->pca_int[2].target;
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target3 = (unsigned long *) &pca->pca_int[3].target;
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*enable0 = *enable1 = *enable2 = *enable3 = 0;
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*target0 = (1UL<<8) | WILDFIRE_QBB(0);
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*target1 = *target2 = *target3 = 0;
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mb();
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*enable0; *enable1; *enable2; *enable3;
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*target0; *target1; *target2; *target3;
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#else
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int i;
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doing_init_irq_hw = 1;
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/* Need to update only once for every possible PCA. */
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for (i = 0; i < WILDFIRE_NR_IRQS; i+=WILDFIRE_IRQ_PER_PCA)
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wildfire_update_irq_hw(i);
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doing_init_irq_hw = 0;
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#endif
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}
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static void
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wildfire_enable_irq(unsigned int irq)
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{
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if (irq < 16)
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i8259a_enable_irq(irq);
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spin_lock(&wildfire_irq_lock);
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set_bit(irq, &cached_irq_mask);
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wildfire_update_irq_hw(irq);
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spin_unlock(&wildfire_irq_lock);
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}
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static void
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wildfire_disable_irq(unsigned int irq)
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{
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if (irq < 16)
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i8259a_disable_irq(irq);
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spin_lock(&wildfire_irq_lock);
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clear_bit(irq, &cached_irq_mask);
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wildfire_update_irq_hw(irq);
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spin_unlock(&wildfire_irq_lock);
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}
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static void
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wildfire_mask_and_ack_irq(unsigned int irq)
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{
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if (irq < 16)
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i8259a_mask_and_ack_irq(irq);
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spin_lock(&wildfire_irq_lock);
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clear_bit(irq, &cached_irq_mask);
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wildfire_update_irq_hw(irq);
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spin_unlock(&wildfire_irq_lock);
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}
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static unsigned int
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wildfire_startup_irq(unsigned int irq)
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{
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wildfire_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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wildfire_end_irq(unsigned int irq)
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{
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#if 0
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if (!irq_desc[irq].action)
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printk("got irq %d\n", irq);
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#endif
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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wildfire_enable_irq(irq);
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}
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static struct hw_interrupt_type wildfire_irq_type = {
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.typename = "WILDFIRE",
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.startup = wildfire_startup_irq,
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.shutdown = wildfire_disable_irq,
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.enable = wildfire_enable_irq,
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.disable = wildfire_disable_irq,
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.ack = wildfire_mask_and_ack_irq,
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.end = wildfire_end_irq,
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};
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static void __init
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wildfire_init_irq_per_pca(int qbbno, int pcano)
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{
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int i, irq_bias;
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unsigned long io_bias;
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static struct irqaction isa_enable = {
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.handler = no_action,
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.name = "isa_enable",
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};
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irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
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+ pcano * WILDFIRE_IRQ_PER_PCA;
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/* Only need the following for first PCI bus per PCA. */
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io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS;
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#if 0
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outb(0, DMA1_RESET_REG + io_bias);
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outb(0, DMA2_RESET_REG + io_bias);
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias);
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outb(0, DMA2_MASK_REG + io_bias);
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#endif
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#if 0
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/* ??? Not sure how to do this, yet... */
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init_i8259a_irqs(); /* ??? */
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#endif
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for (i = 0; i < 16; ++i) {
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if (i == 2)
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continue;
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irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 17:24:36 +08:00
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irq_desc[i+irq_bias].chip = &wildfire_irq_type;
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2005-04-17 06:20:36 +08:00
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}
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irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 17:24:36 +08:00
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irq_desc[36+irq_bias].chip = &wildfire_irq_type;
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2005-04-17 06:20:36 +08:00
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for (i = 40; i < 64; ++i) {
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irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 17:24:36 +08:00
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irq_desc[i+irq_bias].chip = &wildfire_irq_type;
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2005-04-17 06:20:36 +08:00
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}
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setup_irq(32+irq_bias, &isa_enable);
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}
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static void __init
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wildfire_init_irq(void)
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{
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int qbbno, pcano;
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#if 1
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wildfire_init_irq_hw();
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init_i8259a_irqs();
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#endif
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for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) {
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if (WILDFIRE_QBB_EXISTS(qbbno)) {
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for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) {
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if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
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wildfire_init_irq_per_pca(qbbno, pcano);
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}
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}
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}
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}
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}
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static void
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2006-10-08 21:36:08 +08:00
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wildfire_device_interrupt(unsigned long vector)
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2005-04-17 06:20:36 +08:00
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{
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int irq;
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irq = (vector - 0x800) >> 4;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* bits 10-8: source QBB ID
|
|
|
|
|
* bits 7-6: PCA
|
|
|
|
|
* bits 5-0: irq in PCA
|
|
|
|
|
*/
|
|
|
|
|
|
2006-10-08 21:37:32 +08:00
|
|
|
handle_irq(irq);
|
2005-04-17 06:20:36 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PCI Fixup configuration.
|
|
|
|
|
*
|
|
|
|
|
* Summary per PCA (2 PCI or HIPPI buses):
|
|
|
|
|
*
|
|
|
|
|
* Bit Meaning
|
|
|
|
|
* 0-15 ISA
|
|
|
|
|
*
|
|
|
|
|
*32 ISA summary
|
|
|
|
|
*33 SMI
|
|
|
|
|
*34 NMI
|
|
|
|
|
*36 builtin QLogic SCSI (or slot 0 if no IO module)
|
|
|
|
|
*40 Interrupt Line A from slot 2 PCI0
|
|
|
|
|
*41 Interrupt Line B from slot 2 PCI0
|
|
|
|
|
*42 Interrupt Line C from slot 2 PCI0
|
|
|
|
|
*43 Interrupt Line D from slot 2 PCI0
|
|
|
|
|
*44 Interrupt Line A from slot 3 PCI0
|
|
|
|
|
*45 Interrupt Line B from slot 3 PCI0
|
|
|
|
|
*46 Interrupt Line C from slot 3 PCI0
|
|
|
|
|
*47 Interrupt Line D from slot 3 PCI0
|
|
|
|
|
*
|
|
|
|
|
*48 Interrupt Line A from slot 4 PCI1
|
|
|
|
|
*49 Interrupt Line B from slot 4 PCI1
|
|
|
|
|
*50 Interrupt Line C from slot 4 PCI1
|
|
|
|
|
*51 Interrupt Line D from slot 4 PCI1
|
|
|
|
|
*52 Interrupt Line A from slot 5 PCI1
|
|
|
|
|
*53 Interrupt Line B from slot 5 PCI1
|
|
|
|
|
*54 Interrupt Line C from slot 5 PCI1
|
|
|
|
|
*55 Interrupt Line D from slot 5 PCI1
|
|
|
|
|
*56 Interrupt Line A from slot 6 PCI1
|
|
|
|
|
*57 Interrupt Line B from slot 6 PCI1
|
|
|
|
|
*58 Interrupt Line C from slot 6 PCI1
|
|
|
|
|
*50 Interrupt Line D from slot 6 PCI1
|
|
|
|
|
*60 Interrupt Line A from slot 7 PCI1
|
|
|
|
|
*61 Interrupt Line B from slot 7 PCI1
|
|
|
|
|
*62 Interrupt Line C from slot 7 PCI1
|
|
|
|
|
*63 Interrupt Line D from slot 7 PCI1
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* IdSel
|
|
|
|
|
* 0 Cypress Bridge I/O (ISA summary interrupt)
|
|
|
|
|
* 1 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
|
|
|
|
|
* 2 64 bit PCI 0 option slot 2
|
|
|
|
|
* 3 64 bit PCI 0 option slot 3
|
|
|
|
|
* 4 64 bit PCI 1 option slot 4
|
|
|
|
|
* 5 64 bit PCI 1 option slot 5
|
|
|
|
|
* 6 64 bit PCI 1 option slot 6
|
|
|
|
|
* 7 64 bit PCI 1 option slot 7
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static int __init
|
|
|
|
|
wildfire_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
|
|
|
|
{
|
|
|
|
|
static char irq_tab[8][5] __initdata = {
|
|
|
|
|
/*INT INTA INTB INTC INTD */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 0 ISA Bridge */
|
|
|
|
|
{ 36, 36, 36+1, 36+2, 36+3}, /* IdSel 1 SCSI builtin */
|
|
|
|
|
{ 40, 40, 40+1, 40+2, 40+3}, /* IdSel 2 PCI 0 slot 2 */
|
|
|
|
|
{ 44, 44, 44+1, 44+2, 44+3}, /* IdSel 3 PCI 0 slot 3 */
|
|
|
|
|
{ 48, 48, 48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */
|
|
|
|
|
{ 52, 52, 52+1, 52+2, 52+3}, /* IdSel 5 PCI 1 slot 5 */
|
|
|
|
|
{ 56, 56, 56+1, 56+2, 56+3}, /* IdSel 6 PCI 1 slot 6 */
|
|
|
|
|
{ 60, 60, 60+1, 60+2, 60+3}, /* IdSel 7 PCI 1 slot 7 */
|
|
|
|
|
};
|
|
|
|
|
long min_idsel = 0, max_idsel = 7, irqs_per_slot = 5;
|
|
|
|
|
|
|
|
|
|
struct pci_controller *hose = dev->sysdata;
|
|
|
|
|
int irq = COMMON_TABLE_LOOKUP;
|
|
|
|
|
|
|
|
|
|
if (irq > 0) {
|
|
|
|
|
int qbbno = hose->index >> 3;
|
|
|
|
|
int pcano = (hose->index >> 1) & 3;
|
|
|
|
|
irq += (qbbno << 8) + (pcano << 6);
|
|
|
|
|
}
|
|
|
|
|
return irq;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The System Vectors
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector wildfire_mv __initmv = {
|
|
|
|
|
.vector_name = "WILDFIRE",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_WILDFIRE_IO,
|
|
|
|
|
.machine_check = wildfire_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = WILDFIRE_NR_IRQS,
|
|
|
|
|
.device_interrupt = wildfire_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = wildfire_init_arch,
|
|
|
|
|
.init_irq = wildfire_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = common_init_pci,
|
|
|
|
|
.kill_arch = wildfire_kill_arch,
|
|
|
|
|
.pci_map_irq = wildfire_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
|
|
|
|
|
.pa_to_nid = wildfire_pa_to_nid,
|
|
|
|
|
.cpuid_to_nid = wildfire_cpuid_to_nid,
|
|
|
|
|
.node_mem_start = wildfire_node_mem_start,
|
|
|
|
|
.node_mem_size = wildfire_node_mem_size,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(wildfire)
|