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[MIPS] Alchemy: don't unmask timer IRQ early

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Defer the unmasking of the count/compare interrupt (IRQ5) till the
clockevent driver initialization:

- only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the
  ALLINTS macro -- this change is blessed by AMD as I saw it in their own
  patch; :-)

- do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's
  no 32 KHz crystal.

Update the copyrights (taking into account my prior changes), also removing
Pete Popov's old email...

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Sergei Shtylyov 2008-03-24 23:15:50 +03:00 committed by Ralf Baechle
parent a92b05880d
commit 0167509574
3 changed files with 7 additions and 20 deletions
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7
arch/mips/au1000/common/irq.c
View File

@ -1,7 +1,6 @@
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2001, 2007-2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
*
@ -591,7 +590,7 @@ void __init arch_init_irq(void)
imp++;
}
set_c0_status(ALLINTS);
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
/* Board specific IRQ initialization.
*/

8
arch/mips/au1000/common/time.c
View File

@ -1,6 +1,6 @@
/*
*
* Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
* Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
* Copied and modified Carsten Langgaard's time.c
*
* Carsten Langgaard, carstenl@mips.com
@ -265,12 +265,8 @@ void __init plat_time_init(void)
* Check to ensure we really have a 32KHz oscillator before
* we do this.
*/
if (no_au1xxx_32khz) {
if (no_au1xxx_32khz)
printk("WARNING: no 32KHz clock found.\n");
/* Ensure we get CPO_COUNTER interrupts. */
set_c0_status(IE_IRQ5);
}
else {
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
au_writel(0, SYS_TOYWRITE);

12
include/asm-mips/mach-au1x00/au1000.h
View File

@ -3,9 +3,8 @@
* BRIEF MODULE DESCRIPTION
* Include file for Alchemy Semiconductor's Au1k CPU.
*
* Copyright 2000,2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
* Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#ifdef CONFIG_PM
/* no CP0 timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
#else
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
#endif
/*
* SDRAM Register Offsets
*/