forked from luck/tmp_suning_uos_patched
net: phy: dp83869: Add TI dp83869 phy
Add support for the TI DP83869 Gigabit ethernet phy device. The DP83869 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dan Murphy
David S. Miller
parent
4d66c56f7e
commit
01db923e83
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@ -359,6 +359,12 @@ config DP83867_PHY
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---help---
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---help---
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Currently supports the DP83867 PHY.
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Currently supports the DP83867 PHY.
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config DP83869_PHY
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tristate "Texas Instruments DP83869 Gigabit PHY"
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---help---
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Currently supports the DP83869 PHY. This PHY supports copper and
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fiber connections.
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config FIXED_PHY
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config FIXED_PHY
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tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
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tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
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depends on PHYLIB
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depends on PHYLIB
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@ -70,6 +70,7 @@ obj-$(CONFIG_DP83822_PHY) += dp83822.o
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obj-$(CONFIG_DP83TC811_PHY) += dp83tc811.o
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obj-$(CONFIG_DP83TC811_PHY) += dp83tc811.o
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obj-$(CONFIG_DP83848_PHY) += dp83848.o
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obj-$(CONFIG_DP83848_PHY) += dp83848.o
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obj-$(CONFIG_DP83867_PHY) += dp83867.o
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obj-$(CONFIG_DP83867_PHY) += dp83867.o
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obj-$(CONFIG_DP83869_PHY) += dp83869.o
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obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
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obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
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obj-$(CONFIG_ICPLUS_PHY) += icplus.o
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obj-$(CONFIG_ICPLUS_PHY) += icplus.o
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obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
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obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
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431
drivers/net/phy/dp83869.c
Normal file
431
drivers/net/phy/dp83869.c
Normal file
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@ -0,0 +1,431 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Driver for the Texas Instruments DP83869 PHY
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* Copyright (C) 2019 Texas Instruments Inc.
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*/
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#include <linux/ethtool.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <dt-bindings/net/ti-dp83869.h>
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#define DP83869_PHY_ID 0x2000a0f1
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#define DP83869_DEVADDR 0x1f
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#define MII_DP83869_PHYCTRL 0x10
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#define MII_DP83869_MICR 0x12
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#define MII_DP83869_ISR 0x13
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#define DP83869_CTRL 0x1f
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#define DP83869_CFG4 0x1e
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/* Extended Registers */
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#define DP83869_GEN_CFG3 0x0031
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#define DP83869_RGMIICTL 0x0032
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#define DP83869_STRAP_STS1 0x006e
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#define DP83869_RGMIIDCTL 0x0086
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#define DP83869_IO_MUX_CFG 0x0170
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#define DP83869_OP_MODE 0x01df
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#define DP83869_FX_CTRL 0x0c00
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#define DP83869_SW_RESET BIT(15)
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#define DP83869_SW_RESTART BIT(14)
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/* MICR Interrupt bits */
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#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15)
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#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14)
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#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
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#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12)
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#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11)
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#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10)
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#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8)
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#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
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#define MII_DP83869_MICR_WOL_INT_EN BIT(3)
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#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2)
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#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1)
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#define MII_DP83869_MICR_JABBER_INT_EN BIT(0)
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#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \
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BMCR_FULLDPLX | \
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BMCR_SPEED1000)
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/* This is the same bit mask as the BMCR so re-use the BMCR default */
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#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
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/* CFG1 bits */
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#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \
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ADVERTISE_1000FULL | \
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CTL1000_AS_MASTER)
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/* RGMIICTL bits */
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#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1)
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#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0)
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/* STRAP_STS1 bits */
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#define DP83869_STRAP_STS1_RESERVED BIT(11)
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/* PHYCTRL bits */
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#define DP83869_RX_FIFO_SHIFT 12
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#define DP83869_TX_FIFO_SHIFT 14
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/* PHY_CTRL lower bytes 0x48 are declared as reserved */
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#define DP83869_PHY_CTRL_DEFAULT 0x48
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#define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12)
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#define DP83869_PHYCR_RESERVED_MASK BIT(11)
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/* RGMIIDCTL bits */
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#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4
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/* IO_MUX_CFG bits */
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#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
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#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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#define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
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#define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
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/* CFG3 bits */
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#define DP83869_CFG3_PORT_MIRROR_EN BIT(0)
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/* CFG4 bits */
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#define DP83869_INT_OE BIT(7)
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/* OP MODE */
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#define DP83869_OP_MODE_MII BIT(5)
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#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
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enum {
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DP83869_PORT_MIRRORING_KEEP,
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DP83869_PORT_MIRRORING_EN,
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DP83869_PORT_MIRRORING_DIS,
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};
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struct dp83869_private {
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int tx_fifo_depth;
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int rx_fifo_depth;
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int io_impedance;
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int port_mirroring;
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bool rxctrl_strap_quirk;
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int clk_output_sel;
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int mode;
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};
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static int dp83869_ack_interrupt(struct phy_device *phydev)
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{
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int err = phy_read(phydev, MII_DP83869_ISR);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83869_config_intr(struct phy_device *phydev)
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{
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int micr_status = 0;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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micr_status = phy_read(phydev, MII_DP83869_MICR);
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if (micr_status < 0)
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return micr_status;
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micr_status |=
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(MII_DP83869_MICR_AN_ERR_INT_EN |
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MII_DP83869_MICR_SPEED_CHNG_INT_EN |
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MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
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MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
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MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
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MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
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return phy_write(phydev, MII_DP83869_MICR, micr_status);
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}
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return phy_write(phydev, MII_DP83869_MICR, micr_status);
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}
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static int dp83869_config_port_mirroring(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869 = phydev->priv;
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if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
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phy_set_bits_mmd(phydev, DP83869_DEVADDR, DP83869_GEN_CFG3,
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DP83869_CFG3_PORT_MIRROR_EN);
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else
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phy_clear_bits_mmd(phydev, DP83869_DEVADDR, DP83869_GEN_CFG3,
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DP83869_CFG3_PORT_MIRROR_EN);
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return 0;
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}
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#ifdef CONFIG_OF_MDIO
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static int dp83869_of_init(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869 = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *of_node = dev->of_node;
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int ret;
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if (!of_node)
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return -ENODEV;
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dp83869->io_impedance = -EINVAL;
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/* Optional configuration */
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ret = of_property_read_u32(of_node, "ti,clk-output-sel",
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&dp83869->clk_output_sel);
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if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
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dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
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ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
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if (ret == 0) {
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if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
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dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
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return -EINVAL;
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}
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if (of_property_read_bool(of_node, "ti,max-output-impedance"))
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dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
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else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
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dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
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dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
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else
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dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
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if (of_property_read_u32(of_node, "rx-fifo-depth",
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&dp83869->rx_fifo_depth))
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dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
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if (of_property_read_u32(of_node, "tx-fifo-depth",
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&dp83869->tx_fifo_depth))
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dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
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return 0;
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}
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#else
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static int dp83869_of_init(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int dp83869_configure_rgmii(struct phy_device *phydev,
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struct dp83869_private *dp83869)
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{
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int ret, val;
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if (phy_interface_is_rgmii(phydev)) {
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val = phy_read(phydev, MII_DP83869_PHYCTRL);
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if (val < 0)
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return val;
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val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
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val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
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val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
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ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
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if (ret)
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return ret;
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}
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if (dp83869->io_impedance >= 0)
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phy_modify_mmd(phydev, DP83869_DEVADDR,
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DP83869_IO_MUX_CFG,
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DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
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dp83869->io_impedance &
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DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
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return ret;
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}
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static int dp83869_configure_mode(struct phy_device *phydev,
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struct dp83869_private *dp83869)
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{
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int phy_ctrl_val;
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int ret;
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if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
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dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
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return -EINVAL;
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/* Below init sequence for each operational mode is defined in
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* section 9.4.8 of the datasheet.
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*/
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ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
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dp83869->mode);
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if (ret)
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return ret;
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ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
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if (ret)
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return ret;
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phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
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dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
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DP83869_PHY_CTRL_DEFAULT);
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switch (dp83869->mode) {
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case DP83869_RGMII_COPPER_ETHERNET:
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ret = phy_write(phydev, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
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ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
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if (ret)
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return ret;
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ret = dp83869_configure_rgmii(phydev, dp83869);
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if (ret)
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return ret;
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break;
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case DP83869_RGMII_SGMII_BRIDGE:
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phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
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DP83869_SGMII_RGMII_BRIDGE,
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DP83869_SGMII_RGMII_BRIDGE);
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
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if (ret)
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return ret;
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break;
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case DP83869_1000M_MEDIA_CONVERT:
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ret = phy_write(phydev, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
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if (ret)
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return ret;
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break;
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case DP83869_100M_MEDIA_CONVERT:
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ret = phy_write(phydev, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
|
||||||
|
break;
|
||||||
|
case DP83869_SGMII_COPPER_ETHERNET:
|
||||||
|
ret = phy_write(phydev, MII_DP83869_PHYCTRL,
|
||||||
|
phy_ctrl_val);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = phy_write_mmd(phydev, DP83869_DEVADDR,
|
||||||
|
DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
break;
|
||||||
|
case DP83869_RGMII_1000_BASE:
|
||||||
|
case DP83869_RGMII_100_BASE:
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
};
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int dp83869_config_init(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
struct dp83869_private *dp83869 = phydev->priv;
|
||||||
|
int ret, val;
|
||||||
|
|
||||||
|
ret = dp83869_configure_mode(phydev, dp83869);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Enable Interrupt output INT_OE in CFG4 register */
|
||||||
|
if (phy_interrupt_is_valid(phydev)) {
|
||||||
|
val = phy_read(phydev, DP83869_CFG4);
|
||||||
|
val |= DP83869_INT_OE;
|
||||||
|
phy_write(phydev, DP83869_CFG4, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
|
||||||
|
dp83869_config_port_mirroring(phydev);
|
||||||
|
|
||||||
|
/* Clock output selection if muxing property is set */
|
||||||
|
if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
|
||||||
|
phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG,
|
||||||
|
DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
|
||||||
|
dp83869->clk_output_sel <<
|
||||||
|
DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int dp83869_probe(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
struct dp83869_private *dp83869;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!dp83869)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
phydev->priv = dp83869;
|
||||||
|
|
||||||
|
ret = dp83869_of_init(phydev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return dp83869_config_init(phydev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int dp83869_phy_reset(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
usleep_range(10, 20);
|
||||||
|
|
||||||
|
/* Global sw reset sets all registers to default.
|
||||||
|
* Need to set the registers in the PHY to the right config.
|
||||||
|
*/
|
||||||
|
return dp83869_config_init(phydev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct phy_driver dp83869_driver[] = {
|
||||||
|
{
|
||||||
|
PHY_ID_MATCH_MODEL(DP83869_PHY_ID),
|
||||||
|
.name = "TI DP83869",
|
||||||
|
|
||||||
|
.probe = dp83869_probe,
|
||||||
|
.config_init = dp83869_config_init,
|
||||||
|
.soft_reset = dp83869_phy_reset,
|
||||||
|
|
||||||
|
/* IRQ related */
|
||||||
|
.ack_interrupt = dp83869_ack_interrupt,
|
||||||
|
.config_intr = dp83869_config_intr,
|
||||||
|
|
||||||
|
.suspend = genphy_suspend,
|
||||||
|
.resume = genphy_resume,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
module_phy_driver(dp83869_driver);
|
||||||
|
|
||||||
|
static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
|
||||||
|
{ PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
|
||||||
|
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
Loading…
Reference in New Issue
Block a user