From 03bcba73cb3c223ea8ab8d7f33bd85545e47fc75 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 15 Jul 2019 11:55:04 +0100 Subject: [PATCH] MIPS: perf events: handle switch statement falling through warnings Now that we build with -Wimplicit-fallthrough=3, some warnings are produced in the arch/mips perf events code that are promoted to errors: arch/mips/kernel/perf_event_mipsxx.c:792:3: error: this statement may fall through [-Werror=implicit-fallthrough=] arch/mips/kernel/perf_event_mipsxx.c:795:3: error: this statement may fall through [-Werror=implicit-fallthrough=] arch/mips/kernel/perf_event_mipsxx.c:798:3: error: this statement may fall through [-Werror=implicit-fallthrough=] arch/mips/kernel/perf_event_mipsxx.c:1407:6: error: this statement may fall through [-Werror=implicit-fallthrough=] Assume the fall throughs are deliberate amd annotate/eliminate them. Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Gustavo A. R. Silva Cc: Kees Cook Signed-off-by: Stephen Rothwell [paul.burton@mips.com: - Make n signed to fix the loop condition. - Simplify the initialization of n, which should never have a value greater than 4. - Invert conditions in the loop to decrease indentation.] Signed-off-by: Paul Burton --- arch/mips/kernel/perf_event_mipsxx.c | 30 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index d67fb64e908c..f8527793865c 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -793,15 +793,19 @@ static void reset_counters(void *arg) case 4: mipsxx_pmu_write_control(3, 0); mipspmu.write_counter(3, 0); + /* fall through */ case 3: mipsxx_pmu_write_control(2, 0); mipspmu.write_counter(2, 0); + /* fall through */ case 2: mipsxx_pmu_write_control(1, 0); mipspmu.write_counter(1, 0); + /* fall through */ case 1: mipsxx_pmu_write_control(0, 0); mipspmu.write_counter(0, 0); + /* fall through */ } } @@ -1383,7 +1387,7 @@ static int mipsxx_pmu_handle_shared_irq(void) struct perf_sample_data data; unsigned int counters = mipspmu.num_counters; u64 counter; - int handled = IRQ_NONE; + int n, handled = IRQ_NONE; struct pt_regs *regs; if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) @@ -1404,20 +1408,16 @@ static int mipsxx_pmu_handle_shared_irq(void) perf_sample_data_init(&data, 0, 0); - switch (counters) { -#define HANDLE_COUNTER(n) \ - case n + 1: \ - if (test_bit(n, cpuc->used_mask)) { \ - counter = mipspmu.read_counter(n); \ - if (counter & mipspmu.overflow) { \ - handle_associated_event(cpuc, n, &data, regs); \ - handled = IRQ_HANDLED; \ - } \ - } - HANDLE_COUNTER(3) - HANDLE_COUNTER(2) - HANDLE_COUNTER(1) - HANDLE_COUNTER(0) + for (n = counters - 1; n >= 0; n--) { + if (!test_bit(n, cpuc->used_mask)) + continue; + + counter = mipspmu.read_counter(n); + if (!(counter & mipspmu.overflow)) + continue; + + handle_associated_event(cpuc, n, &data, regs); + handled = IRQ_HANDLED; } #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS