forked from luck/tmp_suning_uos_patched
powerpc/85xx: Add Quicc Engine support for p1025rdb
Signed-off-by: Zhicheng Fan <b32736@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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c141b38f86
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@ -26,6 +26,9 @@
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include <asm/fsl_guts.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
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struct mpic *mpic;
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unsigned long root = of_get_flat_dt_root();
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#ifdef CONFIG_QUICC_ENGINE
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struct device_node *np;
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#endif
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if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
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mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
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MPIC_BIG_ENDIAN |
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@ -61,6 +68,18 @@ void __init mpc85xx_rdb_pic_init(void)
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (np) {
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qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
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qe_ic_cascade_high_mpic);
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of_node_put(np);
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} else
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pr_err("%s: Could not find qe-ic node\n", __func__);
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#endif
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}
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/*
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@ -68,7 +87,7 @@ void __init mpc85xx_rdb_pic_init(void)
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*/
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static void __init mpc85xx_rdb_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
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struct device_node *np;
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#endif
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@ -84,6 +103,62 @@ static void __init mpc85xx_rdb_setup_arch(void)
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#endif
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mpc85xx_smp_init();
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!np) {
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pr_err("%s: Could not find Quicc Engine node\n", __func__);
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goto qe_fail;
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}
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qe_reset();
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of_node_put(np);
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np = of_find_node_by_name(NULL, "par_io");
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if (np) {
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struct device_node *ucc;
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par_io_init(np);
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of_node_put(np);
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for_each_node_by_name(ucc, "ucc")
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par_io_of_config(ucc);
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}
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#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
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if (machine_is(p1025_rdb)) {
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struct ccsr_guts_85xx __iomem *guts;
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np = of_find_node_by_name(NULL, "global-utilities");
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if (np) {
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guts = of_iomap(np, 0);
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if (!guts) {
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pr_err("mpc85xx-rdb: could not map global utilities register\n");
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} else {
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/* P1025 has pins muxed for QE and other functions. To
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* enable QE UEC mode, we need to set bit QE0 for UCC1
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* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
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* and QE12 for QE MII management singals in PMUXCR
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* register.
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*/
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setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
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MPC85xx_PMUXCR_QE(3) |
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MPC85xx_PMUXCR_QE(9) |
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MPC85xx_PMUXCR_QE(12));
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iounmap(guts);
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}
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of_node_put(np);
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}
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}
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#endif
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qe_fail:
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#endif /* CONFIG_QUICC_ENGINE */
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printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
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}
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