forked from luck/tmp_suning_uos_patched
spi: Add SPI driver for Mikrotik RB4xx series boards
This driver mediates access between the connected CPLD and other devices on the bus. The m25p80-compatible boot flash and (some models) MMC use regular SPI, bitbanged as required by the SoC. However the SPI-connected CPLD has a two-wire mode, in which two bits are transferred per SPI clock cycle. The second bit is transmitted with the SoC's CS2 pin. Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Bert Vermeulen
Mark Brown
parent
c517d838eb
commit
05aec35787
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@ -429,6 +429,12 @@ config SPI_ROCKCHIP
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The main usecase of this controller is to use spi flash as boot
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device.
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config SPI_RB4XX
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tristate "Mikrotik RB4XX SPI master"
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depends on SPI_MASTER && ATH79
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help
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SPI controller driver for the Mikrotik RB4xx series boards.
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config SPI_RSPI
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tristate "Renesas RSPI/QSPI controller"
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depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
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@ -66,6 +66,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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obj-$(CONFIG_SPI_QUP) += spi-qup.o
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obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
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obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
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spi-s3c24xx-hw-y := spi-s3c24xx.o
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210
drivers/spi/spi-rb4xx.c
Normal file
210
drivers/spi/spi-rb4xx.c
Normal file
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@ -0,0 +1,210 @@
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/*
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* SPI controller driver for the Mikrotik RB4xx boards
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*
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
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*
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* This file was based on the patches for Linux 2.6.27.39 published by
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* MikroTik for their RouterBoard 4xx series devices.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/spi/spi.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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struct rb4xx_spi {
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void __iomem *base;
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struct clk *clk;
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};
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static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
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{
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return __raw_readl(rbspi->base + reg);
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}
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static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
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{
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__raw_writel(value, rbspi->base + reg);
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}
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static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
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{
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u32 regval;
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regval = spi_ioc;
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if (value & BIT(0))
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regval |= AR71XX_SPI_IOC_DO;
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
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}
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static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
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{
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int i;
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for (i = 7; i >= 0; i--)
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do_spi_clk(rbspi, spi_ioc, byte >> i);
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}
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/* The CS2 pin is used to clock in a second bit per clock cycle. */
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static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
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u8 value)
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{
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u32 regval;
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regval = spi_ioc;
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if (value & BIT(1))
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regval |= AR71XX_SPI_IOC_DO;
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if (value & BIT(0))
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regval |= AR71XX_SPI_IOC_CS2;
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
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}
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/* Two bits at a time, msb first */
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static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
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{
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do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
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do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
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do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
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do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
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}
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static void rb4xx_set_cs(struct spi_device *spi, bool enable)
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{
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struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
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/*
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* Setting CS is done along with bitbanging the actual values,
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* since it's all on the same hardware register. However the
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* CPLD needs CS deselected after every command.
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*/
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if (!enable)
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rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
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AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
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}
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static int rb4xx_transfer_one(struct spi_master *master,
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struct spi_device *spi, struct spi_transfer *t)
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{
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struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
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int i;
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u32 spi_ioc;
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u8 *rx_buf;
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const u8 *tx_buf;
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/*
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* Prime the SPI register with the SPI device selected. The m25p80 boot
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* flash and CPLD share the CS0 pin. This works because the CPLD's
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* command set was designed to almost not clash with that of the
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* boot flash.
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*/
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if (spi->chip_select == 2)
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/* MMC */
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spi_ioc = AR71XX_SPI_IOC_CS0;
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else
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/* Boot flash and CPLD */
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spi_ioc = AR71XX_SPI_IOC_CS1;
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tx_buf = t->tx_buf;
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rx_buf = t->rx_buf;
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for (i = 0; i < t->len; ++i) {
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if (t->tx_nbits == SPI_NBITS_DUAL)
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/* CPLD can use two-wire transfers */
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do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
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else
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do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
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if (!rx_buf)
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continue;
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rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
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}
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spi_finalize_current_transfer(master);
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return 0;
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}
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static int rb4xx_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct clk *ahb_clk;
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struct rb4xx_spi *rbspi;
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struct resource *r;
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int err;
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void __iomem *spi_base;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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spi_base = devm_ioremap_resource(&pdev->dev, r);
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if (!spi_base)
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return PTR_ERR(spi_base);
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master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
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if (!master)
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return -ENOMEM;
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ahb_clk = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(ahb_clk))
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return PTR_ERR(ahb_clk);
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master->bus_num = 0;
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master->num_chipselect = 3;
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master->mode_bits = SPI_TX_DUAL;
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master->bits_per_word_mask = BIT(7);
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master->flags = SPI_MASTER_MUST_TX;
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master->transfer_one = rb4xx_transfer_one;
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master->set_cs = rb4xx_set_cs;
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "failed to register SPI master\n");
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return err;
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}
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err = clk_prepare_enable(ahb_clk);
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if (err)
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return err;
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rbspi = spi_master_get_devdata(master);
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rbspi->base = spi_base;
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rbspi->clk = ahb_clk;
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platform_set_drvdata(pdev, rbspi);
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/* Enable SPI */
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rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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return 0;
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}
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static int rb4xx_spi_remove(struct platform_device *pdev)
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{
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struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
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clk_disable_unprepare(rbspi->clk);
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return 0;
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}
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static struct platform_driver rb4xx_spi_drv = {
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.probe = rb4xx_spi_probe,
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.remove = rb4xx_spi_remove,
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.driver = {
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.name = "rb4xx-spi",
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},
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};
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module_platform_driver(rb4xx_spi_drv);
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MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
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MODULE_LICENSE("GPL v2");
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