forked from luck/tmp_suning_uos_patched
Pin control fixes for the v5.2 cycle:
- Fix IRQ setup in the MCP23s08. - Fix pin setup on pins > 31 in the Ocelot driver. - Fix IRQs in the Mediatek driver. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdFd2eAAoJEEEQszewGV1zW8AP/jkDznsyrjSkHOFSjiAjv5aF Yte85bupFkw5y2dMwH/nyF/dQOz34ZwmVA4fuIn/IcY+0+PbdRVJ9dd2suNhO9o3 LULso6rTayKh0+9U+ARS/D9sW73jOvUbAdSCMacGLqwmzaiAUBDdopfQobYq7j3Y ikjeEhHMRoMOJmXOk9JJ9nENBfRS/wGU/G7hALOiuLd/A0X7YkGVP4Y3ViKA77Ec Y7Dcd7fV57XXxh5vvQIbtLrzAY4LlJiFpXyK8p3rf8Fewq2NT2N3oQgQdsap7Dce 8pZxbBr6sw8X++yc2t1OLMkfM6y6iLoHVdwpmOQmU3ZV+3JINWq8Y8oRvH6nOXkM fLBowKEhc1TMFZzujUkDq+tHZw+1ofOJdJHplRsLC9Yy5dP0tEyuyuKhnIByNY63 mH6C4uNYT5h2SPN6aYF1GFdk8b89jQ3r3fdvSAjbEiJ0FTBueuzQlv5iS1Ujhkh7 gTkWVX0MG6faEKn8rEElZVAECf0TlCYov76OG2UF0+nZTbA2aeIjnmnQpcwZhgVl ll1IGiJfKcyqihvbQJv2ZEZliozA3nqon7K9+R68FL3NnJewQcMRx959FG+eMhQw oNp4IPfUSu+4O+m5VjwMeONXHIAMFYQ2MO0idMQGU80BXi+o8gjW/BJYo4WPTlHc bcUfedYYxJzOpYvoKuto =/GFO -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "Sorry to bomb in fixes this late. Maybe I can comfort you by saying it is only driver fixes, and mostly IRQ handling which is something GPIO and pin control drivers never get right. You think it works and then it doesn't. Summary: - Fix IRQ setup in the MCP23s08. - Fix pin setup on pins > 31 in the Ocelot driver. - Fix IRQs in the Mediatek driver" * tag 'pinctrl-v5.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: mediatek: Update cur_mask in mask/mask ops pinctrl: mediatek: Ignore interrupts that are wake only during resume pinctrl: ocelot: fix pinmuxing for pins after 31 pinctrl: ocelot: fix gpio direction for pins after 31 pinctrl: mcp23s08: Fix add_data and irqchip_add_nested call order
This commit is contained in:
Linus Torvalds
commit
061913712d
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@ -113,6 +113,8 @@ static void mtk_eint_mask(struct irq_data *d)
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void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
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eint->regs->mask_set);
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eint->cur_mask[d->hwirq >> 5] &= ~mask;
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writel(mask, reg);
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}
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@ -123,6 +125,8 @@ static void mtk_eint_unmask(struct irq_data *d)
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void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
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eint->regs->mask_clr);
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eint->cur_mask[d->hwirq >> 5] |= mask;
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writel(mask, reg);
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if (eint->dual_edge[d->hwirq])
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@ -217,19 +221,6 @@ static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
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}
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}
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static void mtk_eint_chip_read_mask(const struct mtk_eint *eint,
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void __iomem *base, u32 *buf)
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{
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int port;
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void __iomem *reg;
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for (port = 0; port < eint->hw->ports; port++) {
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reg = base + eint->regs->mask + (port << 2);
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buf[port] = ~readl_relaxed(reg);
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/* Mask is 0 when irq is enabled, and 1 when disabled. */
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}
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}
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static int mtk_eint_irq_request_resources(struct irq_data *d)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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@ -318,7 +309,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct mtk_eint *eint = irq_desc_get_handler_data(desc);
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unsigned int status, eint_num;
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int offset, index, virq;
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int offset, mask_offset, index, virq;
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void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
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int dual_edge, start_level, curr_level;
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@ -328,10 +319,24 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
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status = readl(reg);
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while (status) {
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offset = __ffs(status);
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mask_offset = eint_num >> 5;
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index = eint_num + offset;
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virq = irq_find_mapping(eint->domain, index);
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status &= ~BIT(offset);
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/*
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* If we get an interrupt on pin that was only required
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* for wake (but no real interrupt requested), mask the
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* interrupt (as would mtk_eint_resume do anyway later
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* in the resume sequence).
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*/
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if (eint->wake_mask[mask_offset] & BIT(offset) &&
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!(eint->cur_mask[mask_offset] & BIT(offset))) {
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writel_relaxed(BIT(offset), reg -
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eint->regs->stat +
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eint->regs->mask_set);
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}
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dual_edge = eint->dual_edge[index];
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if (dual_edge) {
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/*
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@ -370,7 +375,6 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
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int mtk_eint_do_suspend(struct mtk_eint *eint)
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{
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mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask);
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mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
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return 0;
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@ -771,6 +771,10 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
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if (ret < 0)
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goto fail;
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ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
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if (ret < 0)
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goto fail;
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mcp->irq_controller =
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device_property_read_bool(dev, "interrupt-controller");
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if (mcp->irq && mcp->irq_controller) {
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@ -812,10 +816,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
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goto fail;
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}
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ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
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if (ret < 0)
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goto fail;
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if (one_regmap_config) {
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mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
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"mcp23xxx-pinctrl.%d", raw_chip_address);
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@ -396,7 +396,7 @@ static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
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return -1;
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}
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#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
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#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
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static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int selector, unsigned int group)
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@ -412,19 +412,21 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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/*
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* f is encoded on two bits.
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* bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
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* ALT1
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* bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
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* ALT[1]
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* This is racy because both registers can't be updated at the same time
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* but it doesn't matter much for now.
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*/
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, pin->pin),
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regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
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BIT(p), f << p);
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, pin->pin),
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regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
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BIT(p), f << (p - 1));
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return 0;
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}
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#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
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static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin, bool input)
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@ -432,7 +434,7 @@ static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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unsigned int p = pin % 32;
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regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, p), BIT(p),
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regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
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input ? 0 : BIT(p));
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return 0;
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@ -445,9 +447,9 @@ static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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unsigned int p = offset % 32;
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, offset),
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regmap_update_bits(info->map, REG_ALT(0, info, offset),
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BIT(p), 0);
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regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, offset),
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regmap_update_bits(info->map, REG_ALT(1, info, offset),
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BIT(p), 0);
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return 0;
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