forked from luck/tmp_suning_uos_patched
mmc: core: expose info about enhanced rpmb support
Following eMMC JEDEC JESD84-B51 standard, an enhanced form of rpmb is supported. What this enhanced mode supports is in addition to be able to write one rpmb or two rpmb frames at a time, 32 frames can be written at a time. Expose this information present in ext csd field so that the user space application that wants to make use of this can do so. Signed-off-by: Krishna Konda <kkonda@codeaurora.org> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1588341189-4371-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -647,6 +647,9 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
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mmc_hostname(card->host),
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card->ext_csd.cmdq_depth);
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}
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card->ext_csd.enhanced_rpmb_supported =
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(card->ext_csd.rel_param &
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EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR);
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}
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out:
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return err;
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@ -786,6 +789,8 @@ MMC_DEV_ATTR(enhanced_area_offset, "%llu\n",
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card->ext_csd.enhanced_area_offset);
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MMC_DEV_ATTR(enhanced_area_size, "%u\n", card->ext_csd.enhanced_area_size);
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MMC_DEV_ATTR(raw_rpmb_size_mult, "%#x\n", card->ext_csd.raw_rpmb_size_mult);
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MMC_DEV_ATTR(enhanced_rpmb_supported, "%#x\n",
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card->ext_csd.enhanced_rpmb_supported);
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MMC_DEV_ATTR(rel_sectors, "%#x\n", card->ext_csd.rel_sectors);
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MMC_DEV_ATTR(ocr, "0x%08x\n", card->ocr);
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MMC_DEV_ATTR(rca, "0x%04x\n", card->rca);
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@ -843,6 +848,7 @@ static struct attribute *mmc_std_attrs[] = {
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&dev_attr_enhanced_area_offset.attr,
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&dev_attr_enhanced_area_size.attr,
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&dev_attr_raw_rpmb_size_mult.attr,
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&dev_attr_enhanced_rpmb_supported.attr,
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&dev_attr_rel_sectors.attr,
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&dev_attr_ocr.attr,
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&dev_attr_rca.attr,
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@ -48,6 +48,7 @@ struct mmc_ext_csd {
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u8 sec_feature_support;
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u8 rel_sectors;
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u8 rel_param;
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bool enhanced_rpmb_supported;
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u8 part_config;
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u8 cache_ctrl;
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u8 rst_n_function;
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@ -325,6 +325,7 @@ static inline bool mmc_ready_for_data(u32 status)
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*/
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#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
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#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4)
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#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
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#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
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