forked from luck/tmp_suning_uos_patched
edac: remove tile driver
The Tile architecture is obsolete and getting removed from the kernel, this driver appears to only be used there, and not on the ARM based successors (Tile-Mx, BlueField), so we should remove it as well. Acked-by: Borislav Petkov <bp@suse.de> Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
e53a05a49e
commit
0833f7634f
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@ -317,14 +317,6 @@ config EDAC_CPC925
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a companion chip to the PowerPC 970 family of
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processors.
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config EDAC_TILE
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tristate "Tilera Memory Controller"
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depends on TILE
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default y
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help
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Support for error detection and correction on the
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Tilera memory controller.
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config EDAC_HIGHBANK_MC
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tristate "Highbank Memory Controller"
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depends on ARCH_HIGHBANK
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@ -64,8 +64,6 @@ obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
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obj-$(CONFIG_EDAC_AMD8111) += amd8111_edac.o
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obj-$(CONFIG_EDAC_AMD8131) += amd8131_edac.o
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obj-$(CONFIG_EDAC_TILE) += tile_edac.o
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obj-$(CONFIG_EDAC_HIGHBANK_MC) += highbank_mc_edac.o
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obj-$(CONFIG_EDAC_HIGHBANK_L2) += highbank_l2_edac.o
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@ -1,265 +0,0 @@
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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* Tilera-specific EDAC driver.
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*
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* This source code is derived from the following driver:
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*
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* Cell MIC driver for ECC counting
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/edac.h>
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#include <hv/hypervisor.h>
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#include <hv/drv_mshim_intf.h>
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#include "edac_module.h"
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#define DRV_NAME "tile-edac"
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/* Number of cs_rows needed per memory controller on TILEPro. */
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#define TILE_EDAC_NR_CSROWS 1
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/* Number of channels per memory controller on TILEPro. */
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#define TILE_EDAC_NR_CHANS 1
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/* Granularity of reported error in bytes on TILEPro. */
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#define TILE_EDAC_ERROR_GRAIN 8
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/* TILE processor has multiple independent memory controllers. */
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struct platform_device *mshim_pdev[TILE_MAX_MSHIMS];
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struct tile_edac_priv {
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int hv_devhdl; /* Hypervisor device handle. */
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int node; /* Memory controller instance #. */
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unsigned int ce_count; /*
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* Correctable-error counter
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* kept by the driver.
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*/
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};
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static void tile_edac_check(struct mem_ctl_info *mci)
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{
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struct tile_edac_priv *priv = mci->pvt_info;
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struct mshim_mem_error mem_error;
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if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error,
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sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) !=
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sizeof(struct mshim_mem_error)) {
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pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure.\n");
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return;
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}
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/* Check if the current error count is different from the saved one. */
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if (mem_error.sbe_count != priv->ce_count) {
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dev_dbg(mci->pdev, "ECC CE err on node %d\n", priv->node);
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priv->ce_count = mem_error.sbe_count;
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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0, 0, 0,
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0, 0, -1,
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mci->ctl_name, "");
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}
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}
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/*
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* Initialize the 'csrows' table within the mci control structure with the
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* addressing of memory.
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*/
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static int tile_edac_init_csrows(struct mem_ctl_info *mci)
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{
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struct csrow_info *csrow = mci->csrows[0];
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struct tile_edac_priv *priv = mci->pvt_info;
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struct mshim_mem_info mem_info;
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struct dimm_info *dimm = csrow->channels[0]->dimm;
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if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
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sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
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sizeof(struct mshim_mem_info)) {
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pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure.\n");
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return -1;
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}
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if (mem_info.mem_ecc)
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dimm->edac_mode = EDAC_SECDED;
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else
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dimm->edac_mode = EDAC_NONE;
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switch (mem_info.mem_type) {
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case DDR2:
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dimm->mtype = MEM_DDR2;
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break;
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case DDR3:
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dimm->mtype = MEM_DDR3;
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break;
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default:
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return -1;
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}
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dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
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dimm->grain = TILE_EDAC_ERROR_GRAIN;
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dimm->dtype = DEV_UNKNOWN;
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return 0;
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}
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static int tile_edac_mc_probe(struct platform_device *pdev)
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{
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char hv_file[32];
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int hv_devhdl;
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[2];
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struct tile_edac_priv *priv;
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int rc;
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sprintf(hv_file, "mshim/%d", pdev->id);
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hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0);
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if (hv_devhdl < 0)
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return -EINVAL;
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/* A TILE MC has a single channel and one chip-select row. */
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = TILE_EDAC_NR_CSROWS;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = TILE_EDAC_NR_CHANS;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
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sizeof(struct tile_edac_priv));
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if (mci == NULL)
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return -ENOMEM;
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priv = mci->pvt_info;
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priv->node = pdev->id;
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priv->hv_devhdl = hv_devhdl;
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mci->pdev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_DDR2;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->mod_name = DRV_NAME;
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#ifdef __tilegx__
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mci->ctl_name = "TILEGx_Memory_Controller";
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#else
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mci->ctl_name = "TILEPro_Memory_Controller";
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#endif
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mci->dev_name = dev_name(&pdev->dev);
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mci->edac_check = tile_edac_check;
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/*
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* Initialize the MC control structure 'csrows' table
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* with the mapping and control information.
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*/
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if (tile_edac_init_csrows(mci)) {
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/* No csrows found. */
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mci->edac_cap = EDAC_FLAG_NONE;
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} else {
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mci->edac_cap = EDAC_FLAG_SECDED;
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}
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platform_set_drvdata(pdev, mci);
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/* Register with EDAC core */
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rc = edac_mc_add_mc(mci);
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if (rc) {
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dev_err(&pdev->dev, "failed to register with EDAC core\n");
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edac_mc_free(mci);
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return rc;
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}
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return 0;
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}
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static int tile_edac_mc_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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if (mci)
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edac_mc_free(mci);
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return 0;
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}
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static struct platform_driver tile_edac_mc_driver = {
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.driver = {
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.name = DRV_NAME,
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},
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.probe = tile_edac_mc_probe,
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.remove = tile_edac_mc_remove,
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};
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/*
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* Driver init routine.
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*/
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static int __init tile_edac_init(void)
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{
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char hv_file[32];
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struct platform_device *pdev;
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int i, err, num = 0;
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/* Only support POLL mode. */
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edac_op_state = EDAC_OPSTATE_POLL;
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err = platform_driver_register(&tile_edac_mc_driver);
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if (err)
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return err;
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for (i = 0; i < TILE_MAX_MSHIMS; i++) {
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/*
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* Not all memory controllers are configured such as in the
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* case of a simulator. So we register only those mshims
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* that are configured by the hypervisor.
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*/
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sprintf(hv_file, "mshim/%d", i);
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if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0)
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continue;
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pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0);
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if (IS_ERR(pdev))
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continue;
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mshim_pdev[i] = pdev;
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num++;
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}
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if (num == 0) {
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platform_driver_unregister(&tile_edac_mc_driver);
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return -ENODEV;
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}
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return 0;
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}
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/*
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* Driver cleanup routine.
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*/
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static void __exit tile_edac_exit(void)
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{
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int i;
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for (i = 0; i < TILE_MAX_MSHIMS; i++) {
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struct platform_device *pdev = mshim_pdev[i];
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if (!pdev)
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continue;
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platform_device_unregister(pdev);
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}
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platform_driver_unregister(&tile_edac_mc_driver);
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}
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module_init(tile_edac_init);
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module_exit(tile_edac_exit);
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