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ARM: S5PV310: Define missing CMU register for CPUFREQ

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This patch adds missing CMU(Clock Management Unit) registers for
updated S5PV310 CPUFREQ driver.

Signed-off-by: Sangwook Ju <sw.ju@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Sangwook Ju 2010-12-22 07:26:40 +09:00 committed by Kukjin Kim
parent 7af36b9787
commit 09dc781e94
1 changed files with 3 additions and 0 deletions
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3
arch/arm/mach-s5pv310/include/mach/regs-clock.h
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@ -89,7 +89,9 @@
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) #define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
@ -100,6 +102,7 @@
#define S5P_APLLCON0_ENABLE_SHIFT (31) #define S5P_APLLCON0_ENABLE_SHIFT (31)
#define S5P_APLLCON0_LOCKED_SHIFT (29) #define S5P_APLLCON0_LOCKED_SHIFT (29)
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
/* CLK_SRC_CPU */ /* CLK_SRC_CPU */
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)