forked from luck/tmp_suning_uos_patched
[WATCHDOG] iTCO_wdt: Cleanup code
Clean-up the iTCO_wdt code so that checkpatch.pl get's happy... Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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@ -35,9 +35,9 @@
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#include "iTCO_vendor.h"
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/* iTCO defines */
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#define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */
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#define TCOBASE acpibase + 0x60 /* TCO base address */
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#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
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#define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */
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#define TCOBASE (acpibase + 0x60) /* TCO base address */
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#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
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/* List of vendor support modes */
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/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
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@ -236,19 +236,19 @@ MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
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/* Address definitions for the TCO */
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/* TCO base address */
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#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60
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#define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
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/* SMI Control and Enable Register */
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#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30
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#define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
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#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */
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#define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
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#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
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#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
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#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
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#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
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#define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
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#define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
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#define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
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#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
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#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
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#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
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#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
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#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
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#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
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#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
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#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
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#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
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/* internal variables */
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static unsigned long is_active;
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