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ARM: imx: fix mx51 ehci setup errors

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This patch completes commit 08406f5 by fixing the following issues, according to
the reference manual:
* MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like H1PM and
  H2PM, not the opposite.
* MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like H1_OC_DIS, not the
  opposite.
* Typos in comments.

Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Benoît Thébaudeau 2012-06-28 16:59:46 +02:00 committed by Sascha Hauer
parent 5cfe82c674
commit 0b87c1d4be
1 changed files with 7 additions and 7 deletions
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14
arch/arm/mach-imx/ehci-imx5.c
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@ -88,11 +88,11 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
else else
v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED) { if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
} else {
/* OC/USBPWR is used */ /* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
} else {
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
} }
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
@ -106,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
else else
v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v |= MXC_OTG_UCTRL_OPM_BIT;
else
v &= ~MXC_OTG_UCTRL_OPM_BIT; v &= ~MXC_OTG_UCTRL_OPM_BIT;
else
v |= MXC_OTG_UCTRL_OPM_BIT;
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
} }
break; break;
@ -124,7 +124,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
} }
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
else else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
@ -157,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
} }
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
else else
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);