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ACPICA: IORT: Update SMMU models for revision C

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ACPICA commit d00a4eb86e64bb4fa70f57ab5e5ca0a4ca2ad8ef

IORT revision C has been published with a number of new SMMU
implementation identifiers; define them.

Link: https://github.com/acpica/acpica/commit/d00a4eb8
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lv Zheng <lv.zheng@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Robin Murphy 2017-07-10 15:22:51 +08:00 committed by Rafael J. Wysocki
parent a7718df2e7
commit 0c2021c047
1 changed files with 10 additions and 2 deletions
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12
include/acpi/actbl2.h
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@ -664,7 +664,7 @@ struct acpi_ibft_target {
* IORT - IO Remapping Table
*
* Conforms to "IO Remapping Table System Software on ARM Platforms",
* Document number: ARM DEN 0049B, October 2015
* Document number: ARM DEN 0049C, May 2017
*
******************************************************************************/
@ -779,6 +779,8 @@ struct acpi_iort_smmu {
#define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */
#define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */
#define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */
#define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */
#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium thunder_x SMMUv2 */
/* Masks for Flags field above */
@ -799,13 +801,19 @@ struct acpi_iort_smmu_v3 {
u32 flags;
u32 reserved;
u64 vatos_address;
u32 model; /* O: generic SMMUv3 */
u32 model;
u32 event_gsiv;
u32 pri_gsiv;
u32 gerr_gsiv;
u32 sync_gsiv;
};
/* Values for Model field above */
#define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */
#define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* hi_silicon Hi161x SMMUv3 */
#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */
/* Masks for Flags field above */
#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)