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[ARM] ohci-pxa27x: use ioremap() and offset for register access

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This avoid the pre-mapping of OHCI controller register space, and the
mapping is made only when necessary (OHCI is probed).

Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao 2008-10-04 12:57:21 +08:00 committed by Russell King
parent 0cb0b0d3c6
commit 0c392ed9a7
2 changed files with 108 additions and 83 deletions
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5
arch/arm/mach-pxa/generic.c
View File

@ -88,11 +88,6 @@ static struct map_desc standard_io_desc[] __initdata = {
.pfn = __phys_to_pfn(0x48000000),
.length = 0x00200000,
.type = MT_DEVICE
}, { /* USB host */
.virtual = 0xf8000000,
.pfn = __phys_to_pfn(0x4c000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* Camera */
.virtual = 0xfa000000,
.pfn = __phys_to_pfn(0x50000000),

186
drivers/usb/host/ohci-pxa27x.c
View File

@ -23,46 +23,43 @@
#include <linux/signal.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/ohci.h>
/*
* UHC: USB Host Controller (OHCI-like) register definitions
*/
#define UHC_BASE_PHYS (0x4C000000)
#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
#define UHCREV (0x0000) /* UHC HCI Spec Revision */
#define UHCHCON (0x0004) /* UHC Host Control Register */
#define UHCCOMS (0x0008) /* UHC Command Status Register */
#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
#define UHCINTE (0x0010) /* UHC Interrupt Enable */
#define UHCINTD (0x0014) /* UHC Interrupt Disable */
#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD (0x0030) /* UHC Done Head */
#define UHCFMI (0x0034) /* UHC Frame Interval */
#define UHCFMR (0x0038) /* UHC Frame Remaining */
#define UHCFMN (0x003C) /* UHC Frame Number */
#define UHCPERS (0x0040) /* UHC Periodic Start */
#define UHCLS (0x0044) /* UHC Low Speed Threshold */
#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
#define UHCRHDA_POTPGT(x) \
(((x) & 0xff) << 24) /* Power On To Power Good Time */
#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
#define UHCRHS (0x0050) /* UHC Root Hub Status */
#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
#define UHCSTAT (0x0060) /* UHC Status Register */
#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
@ -73,7 +70,7 @@
#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
#define UHCHR (0x0064) /* UHC Reset Register */
#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
@ -86,7 +83,7 @@
#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
@ -96,14 +93,20 @@
#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
#define UHCHIT (0x006C) /* UHC Interrupt Test register */
#define PXA_UHC_MAX_PORTNUM 3
#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
struct pxa27x_ohci {
/* must be 1st member here for hcd_to_ohci() to work */
struct ohci_hcd ohci;
static struct clk *usb_clk;
struct device *dev;
struct clk *clk;
void __iomem *mmio_base;
};
#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
/*
PMM_NPS_MODE -- PMM Non-power switching mode
@ -115,30 +118,35 @@ static struct clk *usb_clk;
PMM_PERPORT_MODE -- PMM per port switching mode
Ports are powered individually.
*/
static int pxa27x_ohci_select_pmm( int mode )
static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
{
switch ( mode ) {
uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
switch (mode) {
case PMM_NPS_MODE:
UHCRHDA |= RH_A_NPS;
uhcrhda |= RH_A_NPS;
break;
case PMM_GLOBAL_MODE:
UHCRHDA &= ~(RH_A_NPS & RH_A_PSM);
uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
break;
case PMM_PERPORT_MODE:
UHCRHDA &= ~(RH_A_NPS);
UHCRHDA |= RH_A_PSM;
uhcrhda &= ~(RH_A_NPS);
uhcrhda |= RH_A_PSM;
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
uhcrhdb |= (0x7<<17);
break;
default:
printk( KERN_ERR
"Invalid mode %d, set to non-power switch mode.\n",
mode );
UHCRHDA |= RH_A_NPS;
uhcrhda |= RH_A_NPS;
}
__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
return 0;
}
@ -146,10 +154,11 @@ extern int usb_disabled(void);
/*-------------------------------------------------------------------------*/
static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
struct pxaohci_platform_data *inf)
{
uint32_t uhchr = UHCHR;
uint32_t uhcrhda = UHCRHDA;
uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
if (inf->flags & ENABLE_PORT1)
uhchr &= ~UHCHR_SSEP1;
@ -177,8 +186,17 @@ static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
}
UHCHR = uhchr;
UHCRHDA = uhcrhda;
__raw_writel(uhchr, ohci->mmio_base + UHCHR);
__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
}
static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
{
uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
__raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
udelay(11);
__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
}
#ifdef CONFIG_CPU_PXA27x
@ -187,24 +205,25 @@ extern void pxa27x_clear_otgph(void);
#define pxa27x_clear_otgph() do {} while (0)
#endif
static int pxa27x_start_hc(struct device *dev)
static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
int retval = 0;
struct pxaohci_platform_data *inf;
uint32_t uhchr;
inf = dev->platform_data;
clk_enable(usb_clk);
clk_enable(ohci->clk);
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
pxa27x_reset_hc(ohci);
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR)
uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
__raw_writel(uhchr, ohci->mmio_base + UHCHR);
while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
cpu_relax();
pxa27x_setup_hc(inf);
pxa27x_setup_hc(ohci, inf);
if (inf->init)
retval = inf->init(dev);
@ -212,32 +231,33 @@ static int pxa27x_start_hc(struct device *dev)
if (retval < 0)
return retval;
UHCHR &= ~UHCHR_SSE;
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
__raw_writel(uhchr, ohci->mmio_base + UHCHR);
__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
/* Clear any OTG Pin Hold */
pxa27x_clear_otgph();
return 0;
}
static void pxa27x_stop_hc(struct device *dev)
static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
struct pxaohci_platform_data *inf;
uint32_t uhccoms;
inf = dev->platform_data;
if (inf->exit)
inf->exit(dev);
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
pxa27x_reset_hc(ohci);
UHCCOMS |= 1;
/* Host Controller Reset */
uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
udelay(10);
clk_disable(usb_clk);
clk_disable(ohci->clk);
}
@ -261,7 +281,9 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
int retval, irq;
struct usb_hcd *hcd;
struct pxaohci_platform_data *inf;
struct pxa27x_ohci *ohci;
struct resource *r;
struct clk *usb_clk;
inf = pdev->dev.platform_data;
@ -305,13 +327,19 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
goto err2;
}
if ((retval = pxa27x_start_hc(&pdev->dev)) < 0) {
/* initialize "struct pxa27x_ohci" */
ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
ohci->dev = &pdev->dev;
ohci->clk = usb_clk;
ohci->mmio_base = (void __iomem *)hcd->regs;
if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
pr_debug("pxa27x_start_hc failed");
goto err3;
}
/* Select Power Management Mode */
pxa27x_ohci_select_pmm(inf->port_mode);
pxa27x_ohci_select_pmm(ohci, inf->port_mode);
if (inf->power_budget)
hcd->power_budget = inf->power_budget;
@ -322,7 +350,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
if (retval == 0)
return retval;
pxa27x_stop_hc(&pdev->dev);
pxa27x_stop_hc(ohci, &pdev->dev);
err3:
iounmap(hcd->regs);
err2:
@ -349,12 +377,14 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
*/
void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
{
struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
usb_remove_hcd(hcd);
pxa27x_stop_hc(&pdev->dev);
pxa27x_stop_hc(ohci, &pdev->dev);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
clk_put(usb_clk);
clk_put(ohci->clk);
}
/*-------------------------------------------------------------------------*/
@ -387,7 +417,7 @@ ohci_pxa27x_start (struct usb_hcd *hcd)
static const struct hc_driver ohci_pxa27x_hc_driver = {
.description = hcd_name,
.product_desc = "PXA27x OHCI",
.hcd_priv_size = sizeof(struct ohci_hcd),
.hcd_priv_size = sizeof(struct pxa27x_ohci),
/*
* generic hardware linkage
@ -451,13 +481,13 @@ static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
if (time_before(jiffies, ohci->next_statechange))
if (time_before(jiffies, ohci->ohci.next_statechange))
msleep(5);
ohci->next_statechange = jiffies;
ohci->ohci.next_statechange = jiffies;
pxa27x_stop_hc(&pdev->dev);
pxa27x_stop_hc(ohci, &pdev->dev);
hcd->state = HC_STATE_SUSPENDED;
return 0;
@ -466,14 +496,14 @@ static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_
static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
int status;
if (time_before(jiffies, ohci->next_statechange))
if (time_before(jiffies, ohci->ohci.next_statechange))
msleep(5);
ohci->next_statechange = jiffies;
ohci->ohci.next_statechange = jiffies;
if ((status = pxa27x_start_hc(&pdev->dev)) < 0)
if ((status = pxa27x_start_hc(ohci, &pdev->dev)) < 0)
return status;
ohci_finish_controller_resume(hcd);