forked from luck/tmp_suning_uos_patched
MMC core:
- Prevent re-tuning while serving requests for RPMB partitions - Extend timeout for long read time quirk to support more eMMCs MMC host: - sdhci-acpi: Ensure connected devices are powered when probing - sdhci-pci|acpi: Remove unreliable MMC_CAP_BUS_WIDTH_TEST for Intel HWs - dw_mmc: Correct the assigning of max_blk_size - dw_mmc-rockchip: Allow RPMB partitions to be created - dw_mmc-rockchip: Set the drive phase properly -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXRq1wAAoJEP4mhCVzWIwpKa0QAId0gcmR5EF45FHYdNP50TgJ EgJa8xFZiBXC/RZbcDYBOfNVcQ+RqvCs4K5PxJcpleARA7MtCcbwWpKynHG/2cdR xbZbzuuMd4jKS7AO6kC1Rww370XTRhtXAlkO1w/KWvnC79wV86EgIxxl8adBycw7 68JFmjrcDTyBq63G0jHZlUzA8mVxl+k9Jb3lW1+FnsGMCV7R4dOK58rwp3z7ITwl r4sSQGN6STwlav3tLlurNi/7Wd9VfHjbuuwSR9oIc11hRzBNNL+I2Runk/4lfD6q 52S4OYoqPiZrMheYonQ6zVAjm9MVWLAMId6AbJXlx8m42qbq2q2o4gv4csGjKiNr e8ZaHRw8FYRL8A4UewYcewPxJfXkJSV81KNKQYS1jn94zfPspffln73VM1Sbqmu8 tg89C1CYShAS0IcIyKk3XCBocq6JARIF+M7mE3FTZd3yfBd6hBbjUbv9ufKnbsxJ lSG9jISCYaqsoc4SLK/hBEypN68otLKDm7Jl8VcPj351f5NDlj0hv56scqt3HbAk hcPUYtHc5+6vsQ1mIQRC+NmH9qacChq8JfLHej7HB+hSCJZUp35QB0Zr6oTmv4G4 9mUY/J6++9fGQtcWWAyNcVOuZUjGSxiSDm6wgtZMJZDYUFECXDdPEYRatBIMa2Ul 4bbcKYEbqdC8Cn2q5FZn =zHa6 -----END PGP SIGNATURE----- Merge tag 'mmc-v4.7-rc1' of git://git.linaro.org/people/ulf.hansson/mmc Pull MMC fixes from Ulf Hansson: "Here are some mmc fixes intended for v4.7 rc1. They are based on a commit earlier in the merge window and have been tested in linux-next for a while. MMC core: - Prevent re-tuning while serving requests for RPMB partitions - Extend timeout for long read time quirk to support more eMMCs MMC host: - sdhci-acpi: Ensure connected devices are powered when probing - sdhci-pci|acpi: Remove unreliable MMC_CAP_BUS_WIDTH_TEST for Intel HWs - dw_mmc: Correct the assigning of max_blk_size - dw_mmc-rockchip: Allow RPMB partitions to be created - dw_mmc-rockchip: Set the drive phase properly" * tag 'mmc-v4.7-rc1' of git://git.linaro.org/people/ulf.hansson/mmc: mmc: sdhci-acpi: Remove MMC_CAP_BUS_WIDTH_TEST for Intel controllers mmc: sdhci-pci: Remove MMC_CAP_BUS_WIDTH_TEST for Intel controllers mmc: longer timeout for long read time quirk mmc: dw_mmc: rockchip: Set the drive phase properly mmc: dw_mmc: fix the wrong max_blk_size mmc: dw_mmc-rockchip: add MMC_CAP_CMD23 capabilities mmc: sdhci-acpi: Ensure connected devices are powered when probing ACPI / PM: Export acpi_device_fix_up_power() mmc: block: Pause re-tuning while switched to the RPMB partition mmc: block: Always switch back to main area after RPMB access mmc: core: Add a facility to "pause" re-tuning
This commit is contained in:
Linus Torvalds
commit
0e77816e09
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@ -319,6 +319,7 @@ int acpi_device_fix_up_power(struct acpi_device *device)
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return ret;
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}
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EXPORT_SYMBOL_GPL(acpi_device_fix_up_power);
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int acpi_device_update_power(struct acpi_device *device, int *state_p)
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{
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@ -618,6 +618,10 @@ static int mmc_blk_ioctl_cmd(struct block_device *bdev,
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ioc_err = __mmc_blk_ioctl_cmd(card, md, idata);
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/* Always switch back to main area after RPMB access */
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if (md->area_type & MMC_BLK_DATA_AREA_RPMB)
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mmc_blk_part_switch(card, dev_get_drvdata(&card->dev));
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mmc_put_card(card);
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err = mmc_blk_ioctl_copy_to_user(ic_ptr, idata);
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@ -685,6 +689,10 @@ static int mmc_blk_ioctl_multi_cmd(struct block_device *bdev,
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for (i = 0; i < num_of_cmds && !ioc_err; i++)
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ioc_err = __mmc_blk_ioctl_cmd(card, md, idata[i]);
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/* Always switch back to main area after RPMB access */
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if (md->area_type & MMC_BLK_DATA_AREA_RPMB)
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mmc_blk_part_switch(card, dev_get_drvdata(&card->dev));
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mmc_put_card(card);
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/* copy to user if data and response */
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@ -748,16 +756,25 @@ static inline int mmc_blk_part_switch(struct mmc_card *card,
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if (mmc_card_mmc(card)) {
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u8 part_config = card->ext_csd.part_config;
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if (md->part_type == EXT_CSD_PART_CONFIG_ACC_RPMB)
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mmc_retune_pause(card->host);
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part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
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part_config |= md->part_type;
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ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_PART_CONFIG, part_config,
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card->ext_csd.part_time);
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if (ret)
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if (ret) {
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if (md->part_type == EXT_CSD_PART_CONFIG_ACC_RPMB)
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mmc_retune_unpause(card->host);
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return ret;
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}
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card->ext_csd.part_config = part_config;
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if (main_md->part_curr == EXT_CSD_PART_CONFIG_ACC_RPMB)
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mmc_retune_unpause(card->host);
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}
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main_md->part_curr = md->part_type;
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@ -2519,11 +2536,12 @@ static const struct mmc_fixup blk_fixups[] =
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MMC_QUIRK_BLK_NO_CMD23),
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/*
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* Some Micron MMC cards needs longer data read timeout than
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* indicated in CSD.
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* Some MMC cards need longer data read timeout than indicated in CSD.
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*/
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MMC_FIXUP(CID_NAME_ANY, CID_MANFID_MICRON, 0x200, add_quirk_mmc,
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MMC_QUIRK_LONG_READ_TIME),
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MMC_FIXUP("008GE0", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
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MMC_QUIRK_LONG_READ_TIME),
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/*
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* On these Samsung MoviNAND parts, performing secure erase or
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@ -875,11 +875,11 @@ void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card)
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/*
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* Some cards require longer data read timeout than indicated in CSD.
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* Address this by setting the read timeout to a "reasonably high"
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* value. For the cards tested, 300ms has proven enough. If necessary,
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* value. For the cards tested, 600ms has proven enough. If necessary,
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* this value can be increased if other problematic cards require this.
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*/
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if (mmc_card_long_read_time(card) && data->flags & MMC_DATA_READ) {
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data->timeout_ns = 300000000;
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data->timeout_ns = 600000000;
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data->timeout_clks = 0;
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}
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@ -68,8 +68,32 @@ void mmc_retune_enable(struct mmc_host *host)
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jiffies + host->retune_period * HZ);
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}
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/*
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* Pause re-tuning for a small set of operations. The pause begins after the
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* next command and after first doing re-tuning.
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*/
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void mmc_retune_pause(struct mmc_host *host)
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{
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if (!host->retune_paused) {
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host->retune_paused = 1;
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mmc_retune_needed(host);
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mmc_retune_hold(host);
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}
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}
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EXPORT_SYMBOL(mmc_retune_pause);
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void mmc_retune_unpause(struct mmc_host *host)
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{
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if (host->retune_paused) {
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host->retune_paused = 0;
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mmc_retune_release(host);
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}
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}
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EXPORT_SYMBOL(mmc_retune_unpause);
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void mmc_retune_disable(struct mmc_host *host)
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{
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mmc_retune_unpause(host);
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host->can_retune = 0;
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del_timer_sync(&host->retune_timer);
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host->retune_now = 0;
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@ -66,6 +66,70 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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/* Make sure we use phases which we can enumerate with */
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if (!IS_ERR(priv->sample_clk))
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clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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/*
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* Set the drive phase offset based on speed mode to achieve hold times.
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*
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* NOTE: this is _not_ a value that is dynamically tuned and is also
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* _not_ a value that will vary from board to board. It is a value
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* that could vary between different SoC models if they had massively
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* different output clock delays inside their dw_mmc IP block (delay_o),
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* but since it's OK to overshoot a little we don't need to do complex
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* calculations and can pick values that will just work for everyone.
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*
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* When picking values we'll stick with picking 0/90/180/270 since
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* those can be made very accurately on all known Rockchip SoCs.
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*
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* Note that these values match values from the DesignWare Databook
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* tables for the most part except for SDR12 and "ID mode". For those
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* two modes the databook calculations assume a clock in of 50MHz. As
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* seen above, we always use a clock in rate that is exactly the
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* card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
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* back out before the controller sees it).
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*
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* From measurement of a single device, it appears that delay_o is
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* about .5 ns. Since we try to leave a bit of margin, it's expected
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* that numbers here will be fine even with much larger delay_o
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* (the 1.4 ns assumed by the DesignWare Databook would result in the
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* same results, for instance).
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*/
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if (!IS_ERR(priv->drv_clk)) {
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int phase;
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/*
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* In almost all cases a 90 degree phase offset will provide
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* sufficient hold times across all valid input clock rates
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* assuming delay_o is not absurd for a given SoC. We'll use
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* that as a default.
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*/
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phase = 90;
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switch (ios->timing) {
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case MMC_TIMING_MMC_DDR52:
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/*
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* Since clock in rate with MMC_DDR52 is doubled when
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* bus width is 8 we need to double the phase offset
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* to get the same timings.
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*/
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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phase = 180;
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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/*
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* In the case of 150 MHz clock (typical max for
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* Rockchip SoCs), 90 degree offset will add a delay
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* of 1.67 ns. That will meet min hold time of .8 ns
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* as long as clock output delay is < .87 ns. On
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* SoCs measured this seems to be OK, but it doesn't
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* hurt to give margin here, so we use 180.
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*/
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phase = 180;
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break;
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}
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clk_set_phase(priv->drv_clk, phase);
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}
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}
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#define NUM_PHASES 360
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@ -233,10 +297,10 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
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/* Common capabilities of RK3288 SoC */
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static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
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MMC_CAP_ERASE,
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MMC_CAP_ERASE,
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MMC_CAP_ERASE,
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MMC_CAP_ERASE,
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MMC_CAP_ERASE | MMC_CAP_CMD23,
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MMC_CAP_ERASE | MMC_CAP_CMD23,
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MMC_CAP_ERASE | MMC_CAP_CMD23,
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MMC_CAP_ERASE | MMC_CAP_CMD23,
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};
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static const struct dw_mci_drv_data rk2928_drv_data = {
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@ -2595,13 +2595,13 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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/* Useful defaults if platform data is unset. */
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if (host->use_dma == TRANS_MODE_IDMAC) {
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mmc->max_segs = host->ring_size;
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mmc->max_blk_size = 65536;
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mmc->max_blk_size = 65535;
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mmc->max_seg_size = 0x1000;
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mmc->max_req_size = mmc->max_seg_size * host->ring_size;
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mmc->max_blk_count = mmc->max_req_size / 512;
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} else if (host->use_dma == TRANS_MODE_EDMAC) {
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mmc->max_segs = 64;
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mmc->max_blk_size = 65536;
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mmc->max_blk_size = 65535;
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mmc->max_blk_count = 65535;
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mmc->max_req_size =
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mmc->max_blk_size * mmc->max_blk_count;
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@ -2609,7 +2609,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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} else {
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/* TRANS_MODE_PIO */
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mmc->max_segs = 64;
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mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
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mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
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mmc->max_blk_count = 512;
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mmc->max_req_size = mmc->max_blk_size *
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mmc->max_blk_count;
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@ -274,7 +274,7 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
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.chip = &sdhci_acpi_chip_int,
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.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
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MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
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MMC_CAP_BUS_WIDTH_TEST | MMC_CAP_WAIT_WHILE_BUSY,
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MMC_CAP_WAIT_WHILE_BUSY,
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.caps2 = MMC_CAP2_HC_ERASE_SZ,
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.flags = SDHCI_ACPI_RUNTIME_PM,
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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@ -289,7 +289,7 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
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SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
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.caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
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MMC_CAP_BUS_WIDTH_TEST | MMC_CAP_WAIT_WHILE_BUSY,
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MMC_CAP_WAIT_WHILE_BUSY,
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.flags = SDHCI_ACPI_RUNTIME_PM,
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.pm_caps = MMC_PM_KEEP_POWER,
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.probe_slot = sdhci_acpi_sdio_probe_slot,
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@ -301,7 +301,7 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
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SDHCI_QUIRK2_STOP_WITH_TC,
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.caps = MMC_CAP_BUS_WIDTH_TEST | MMC_CAP_WAIT_WHILE_BUSY,
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.caps = MMC_CAP_WAIT_WHILE_BUSY,
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.probe_slot = sdhci_acpi_sd_probe_slot,
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};
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@ -378,7 +378,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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acpi_handle handle = ACPI_HANDLE(dev);
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struct acpi_device *device;
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struct acpi_device *device, *child;
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struct sdhci_acpi_host *c;
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struct sdhci_host *host;
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struct resource *iomem;
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@ -390,6 +390,11 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
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if (acpi_bus_get_device(handle, &device))
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return -ENODEV;
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/* Power on the SDHCI controller and its children */
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acpi_device_fix_up_power(device);
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list_for_each_entry(child, &device->children, node)
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acpi_device_fix_up_power(child);
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if (acpi_bus_get_status(device) || !device->status.present)
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return -ENODEV;
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@ -356,7 +356,6 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
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MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
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MMC_CAP_BUS_WIDTH_TEST |
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MMC_CAP_WAIT_WHILE_BUSY;
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slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
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slot->hw_reset = sdhci_pci_int_hw_reset;
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@ -372,15 +371,13 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
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static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
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MMC_CAP_BUS_WIDTH_TEST |
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MMC_CAP_WAIT_WHILE_BUSY;
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return 0;
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}
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static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
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MMC_CAP_WAIT_WHILE_BUSY;
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slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
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slot->cd_con_id = NULL;
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slot->cd_idx = 0;
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slot->cd_override_level = true;
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|
|
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@ -329,6 +329,7 @@ struct mmc_host {
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unsigned int can_retune:1; /* re-tuning can be used */
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unsigned int doing_retune:1; /* re-tuning in progress */
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unsigned int retune_now:1; /* do re-tuning at next req */
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unsigned int retune_paused:1; /* re-tuning is temporarily disabled */
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int rescan_disable; /* disable card detection */
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int rescan_entered; /* used with nonremovable devices */
|
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@ -526,4 +527,7 @@ static inline void mmc_retune_recheck(struct mmc_host *host)
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host->retune_now = 1;
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}
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void mmc_retune_pause(struct mmc_host *host);
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void mmc_retune_unpause(struct mmc_host *host);
|
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#endif /* LINUX_MMC_HOST_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user