forked from luck/tmp_suning_uos_patched
amd64_edac: add EDAC core-related initializers
Borislav: - add a amd64_free_mc_sibling_devices() helper instead of opencoding the release-path. - fix/cleanup comments - fix function return value patterns - cleanup debug calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
d27bf6fa36
commit
0ec449ee95
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@ -2455,4 +2455,319 @@ int amd64_process_error_info(struct mem_ctl_info *mci,
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}
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EXPORT_SYMBOL_GPL(amd64_process_error_info);
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/*
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* The main polling 'check' function, called FROM the edac core to perform the
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* error checking and if an error is encountered, error processing.
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*/
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static void amd64_check(struct mem_ctl_info *mci)
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{
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struct amd64_error_info_regs info;
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if (amd64_get_error_info(mci, &info))
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amd64_process_error_info(mci, &info, 1);
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}
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/*
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* Input:
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* 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer
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* 2) AMD Family index value
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*
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* Ouput:
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* Upon return of 0, the following filled in:
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*
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* struct pvt->addr_f1_ctl
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* struct pvt->misc_f3_ctl
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*
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* Filled in with related device funcitions of 'dram_f2_ctl'
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* These devices are "reserved" via the pci_get_device()
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*
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* Upon return of 1 (error status):
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*
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* Nothing reserved
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*/
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static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx)
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{
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const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx];
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/* Reserve the ADDRESS MAP Device */
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pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor,
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amd64_dev->addr_f1_ctl,
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pvt->dram_f2_ctl);
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if (!pvt->addr_f1_ctl) {
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amd64_printk(KERN_ERR, "error address map device not found: "
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"vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl);
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return 1;
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}
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/* Reserve the MISC Device */
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pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor,
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amd64_dev->misc_f3_ctl,
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pvt->dram_f2_ctl);
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if (!pvt->misc_f3_ctl) {
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pci_dev_put(pvt->addr_f1_ctl);
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pvt->addr_f1_ctl = NULL;
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amd64_printk(KERN_ERR, "error miscellaneous device not found: "
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"vendor %x device 0x%x (broken BIOS?)\n",
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PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl);
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return 1;
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}
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debugf1(" Addr Map device PCI Bus ID:\t%s\n",
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pci_name(pvt->addr_f1_ctl));
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debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n",
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pci_name(pvt->dram_f2_ctl));
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debugf1(" Misc device PCI Bus ID:\t%s\n",
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pci_name(pvt->misc_f3_ctl));
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return 0;
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}
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static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt)
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{
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pci_dev_put(pvt->addr_f1_ctl);
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pci_dev_put(pvt->misc_f3_ctl);
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}
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/*
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* Retrieve the hardware registers of the memory controller (this includes the
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* 'Address Map' and 'Misc' device regs)
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*/
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static void amd64_read_mc_registers(struct amd64_pvt *pvt)
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{
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u64 msr_val;
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int dram, err = 0;
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/*
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* Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
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* those are Read-As-Zero
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*/
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rdmsrl(MSR_K8_TOP_MEM1, msr_val);
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pvt->top_mem = msr_val >> 23;
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debugf0(" TOP_MEM=0x%08llx\n", pvt->top_mem);
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/* check first whether TOP_MEM2 is enabled */
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rdmsrl(MSR_K8_SYSCFG, msr_val);
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if (msr_val & (1U << 21)) {
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rdmsrl(MSR_K8_TOP_MEM2, msr_val);
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pvt->top_mem2 = msr_val >> 23;
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debugf0(" TOP_MEM2=0x%08llx\n", pvt->top_mem2);
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} else
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debugf0(" TOP_MEM2 disabled.\n");
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amd64_cpu_display_info(pvt);
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap);
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if (err)
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goto err_reg;
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if (pvt->ops->read_dram_ctl_register)
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pvt->ops->read_dram_ctl_register(pvt);
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for (dram = 0; dram < DRAM_REG_COUNT; dram++) {
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/*
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* Call CPU specific READ function to get the DRAM Base and
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* Limit values from the DCT.
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*/
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pvt->ops->read_dram_base_limit(pvt, dram);
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/*
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* Only print out debug info on rows with both R and W Enabled.
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* Normal processing, compiler should optimize this whole 'if'
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* debug output block away.
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*/
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if (pvt->dram_rw_en[dram] != 0) {
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debugf1(" DRAM_BASE[%d]: 0x%8.08x-%8.08x "
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"DRAM_LIMIT: 0x%8.08x-%8.08x\n",
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dram,
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(u32)(pvt->dram_base[dram] >> 32),
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(u32)(pvt->dram_base[dram] & 0xFFFFFFFF),
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(u32)(pvt->dram_limit[dram] >> 32),
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(u32)(pvt->dram_limit[dram] & 0xFFFFFFFF));
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debugf1(" IntlvEn=%s %s %s "
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"IntlvSel=%d DstNode=%d\n",
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pvt->dram_IntlvEn[dram] ?
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"Enabled" : "Disabled",
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(pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W",
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(pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R",
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pvt->dram_IntlvSel[dram],
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pvt->dram_DstNode[dram]);
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}
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}
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amd64_read_dct_base_mask(pvt);
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err = pci_read_config_dword(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar);
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if (err)
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goto err_reg;
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amd64_read_dbam_reg(pvt);
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err = pci_read_config_dword(pvt->misc_f3_ctl,
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F10_ONLINE_SPARE, &pvt->online_spare);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0);
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if (err)
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goto err_reg;
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if (!dct_ganging_enabled(pvt)) {
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1,
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&pvt->dclr1);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCHR_1,
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&pvt->dchr1);
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if (err)
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goto err_reg;
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}
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amd64_dump_misc_regs(pvt);
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err_reg:
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debugf0("Reading an MC register failed\n");
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}
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/*
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* NOTE: CPU Revision Dependent code
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*
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* Input:
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* @csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1)
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* k8 private pointer to -->
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* DRAM Bank Address mapping register
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* node_id
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* DCL register where dual_channel_active is
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*
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* The DBAM register consists of 4 sets of 4 bits each definitions:
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*
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* Bits: CSROWs
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* 0-3 CSROWs 0 and 1
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* 4-7 CSROWs 2 and 3
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* 8-11 CSROWs 4 and 5
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* 12-15 CSROWs 6 and 7
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*
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* Values range from: 0 to 15
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* The meaning of the values depends on CPU revision and dual-channel state,
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* see relevant BKDG more info.
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*
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* The memory controller provides for total of only 8 CSROWs in its current
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* architecture. Each "pair" of CSROWs normally represents just one DIMM in
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* single channel or two (2) DIMMs in dual channel mode.
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*
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* The following code logic collapses the various tables for CSROW based on CPU
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* revision.
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*
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* Returns:
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* The number of PAGE_SIZE pages on the specified CSROW number it
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* encompasses
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*
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*/
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static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
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{
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u32 dram_map, nr_pages;
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/*
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* The math on this doesn't look right on the surface because x/2*4 can
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* be simplified to x*2 but this expression makes use of the fact that
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* it is integral math where 1/2=0. This intermediate value becomes the
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* number of bits to shift the DBAM register to extract the proper CSROW
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* field.
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*/
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dram_map = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;
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nr_pages = pvt->ops->dbam_map_to_pages(pvt, dram_map);
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/*
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* If dual channel then double the memory size of single channel.
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* Channel count is 1 or 2
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*/
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nr_pages <<= (pvt->channel_count - 1);
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debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, dram_map);
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debugf0(" nr_pages= %u channel-count = %d\n",
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nr_pages, pvt->channel_count);
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return nr_pages;
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}
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/*
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* Initialize the array of csrow attribute instances, based on the values
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* from pci config hardware registers.
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*/
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static int amd64_init_csrows(struct mem_ctl_info *mci)
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{
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struct csrow_info *csrow;
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struct amd64_pvt *pvt;
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u64 input_addr_min, input_addr_max, sys_addr;
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int i, err = 0, empty = 1;
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pvt = mci->pvt_info;
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg,
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(pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"
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);
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for (i = 0; i < CHIPSELECT_COUNT; i++) {
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csrow = &mci->csrows[i];
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if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {
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debugf1("----CSROW %d EMPTY for node %d\n", i,
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pvt->mc_node_id);
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continue;
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}
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debugf1("----CSROW %d VALID for MC node %d\n",
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i, pvt->mc_node_id);
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empty = 0;
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csrow->nr_pages = amd64_csrow_nr_pages(i, pvt);
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find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
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sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
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csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
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sys_addr = input_addr_to_sys_addr(mci, input_addr_max);
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csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT);
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csrow->page_mask = ~mask_from_dct_mask(pvt, i);
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/* 8 bytes of resolution */
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csrow->mtype = amd64_determine_memory_type(pvt);
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debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i);
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debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n",
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(unsigned long)input_addr_min,
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(unsigned long)input_addr_max);
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debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n",
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(unsigned long)sys_addr, csrow->page_mask);
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debugf1(" nr_pages: %u first_page: 0x%lx "
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"last_page: 0x%lx\n",
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(unsigned)csrow->nr_pages,
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csrow->first_page, csrow->last_page);
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/*
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* determine whether CHIPKILL or JUST ECC or NO ECC is operating
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*/
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if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE)
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csrow->edac_mode =
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(pvt->nbcfg & K8_NBCFG_CHIPKILL) ?
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EDAC_S4ECD4ED : EDAC_SECDED;
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else
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csrow->edac_mode = EDAC_NONE;
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}
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return empty;
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}
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