forked from luck/tmp_suning_uos_patched
drm/radeon: switch to a finer grained reset for evergreen
No change in functionality as we currently set all the reset flags. Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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71e3d1578c
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0ecebb9e0d
@ -2306,15 +2306,13 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
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return radeon_ring_test_lockup(rdev, ring);
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return radeon_ring_test_lockup(rdev, ring);
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}
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}
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static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
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{
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{
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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u32 grbm_reset = 0, tmp;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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return;
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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@ -2331,27 +2329,10 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(CP_BUSY_STAT));
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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RREG32(CP_STAT));
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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/* Disable DMA */
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tmp = RREG32(DMA_RB_CNTL);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, tmp);
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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/* reset all the gfx blocks */
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/* reset all the gfx blocks */
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grbm_reset = (SOFT_RESET_CP |
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grbm_reset = (SOFT_RESET_CP |
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SOFT_RESET_CB |
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SOFT_RESET_CB |
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@ -2372,8 +2353,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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udelay(50);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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WREG32(GRBM_SOFT_RESET, 0);
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(void)RREG32(GRBM_SOFT_RESET);
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(void)RREG32(GRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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@ -2390,15 +2370,65 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(CP_BUSY_STAT));
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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RREG32(CP_STAT));
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}
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static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
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{
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u32 tmp;
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if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
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return;
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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RREG32(DMA_STATUS_REG));
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/* Disable DMA */
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tmp = RREG32(DMA_RB_CNTL);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, tmp);
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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}
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static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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{
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struct evergreen_mc_save save;
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if (reset_mask == 0)
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return 0;
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dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
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evergreen_gpu_soft_reset_gfx(rdev);
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if (reset_mask & RADEON_RESET_DMA)
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evergreen_gpu_soft_reset_dma(rdev);
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/* Wait a little for things to settle down */
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udelay(50);
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evergreen_mc_resume(rdev, &save);
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evergreen_mc_resume(rdev, &save);
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return 0;
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return 0;
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}
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}
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int evergreen_asic_reset(struct radeon_device *rdev)
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int evergreen_asic_reset(struct radeon_device *rdev)
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{
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{
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return evergreen_gpu_soft_reset(rdev);
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return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
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RADEON_RESET_COMPUTE |
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RADEON_RESET_DMA));
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}
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}
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/* Interrupts */
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/* Interrupts */
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@ -2037,5 +2037,6 @@
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# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
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# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
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# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
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# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
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#define DMA_STATUS_REG 0xd034
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#define DMA_STATUS_REG 0xd034
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# define DMA_IDLE (1 << 0)
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#endif
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#endif
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