forked from luck/tmp_suning_uos_patched
iwlwifi: pcie: fix memory leaks in iwl_pcie_ctxt_info_gen3_init
In iwl_pcie_ctxt_info_gen3_init there are cases that the allocated dma
memory is leaked in case of error.
DMA memories prph_scratch, prph_info, and ctxt_info_gen3 are allocated
and initialized to be later assigned to trans_pcie. But in any error case
before such assignment the allocated memories should be released.
First of such error cases happens when iwl_pcie_init_fw_sec fails.
Current implementation correctly releases prph_scratch. But in two
sunsequent error cases where dma_alloc_coherent may fail, such
releases are missing.
This commit adds release for prph_scratch when allocation for
prph_info fails, and adds releases for prph_scratch and prph_info when
allocation for ctxt_info_gen3 fails.
Fixes: 2ee8240262
("iwlwifi: pcie: support context information for 22560 devices")
Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
parent
b4b814fec1
commit
0f4f199443
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@ -107,13 +107,9 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
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if (ret) {
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dma_free_coherent(trans->dev,
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sizeof(*prph_scratch),
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prph_scratch,
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trans_pcie->prph_scratch_dma_addr);
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return ret;
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}
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if (ret)
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goto err_free_prph_scratch;
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/* Allocate prph information
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* currently we don't assign to the prph info anything, but it would get
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@ -121,16 +117,20 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
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&trans_pcie->prph_info_dma_addr,
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GFP_KERNEL);
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if (!prph_info)
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return -ENOMEM;
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if (!prph_info) {
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ret = -ENOMEM;
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goto err_free_prph_scratch;
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}
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/* Allocate context info */
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ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
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sizeof(*ctxt_info_gen3),
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&trans_pcie->ctxt_info_dma_addr,
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GFP_KERNEL);
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if (!ctxt_info_gen3)
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return -ENOMEM;
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if (!ctxt_info_gen3) {
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ret = -ENOMEM;
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goto err_free_prph_info;
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}
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ctxt_info_gen3->prph_info_base_addr =
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cpu_to_le64(trans_pcie->prph_info_dma_addr);
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@ -186,6 +186,20 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
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return 0;
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err_free_prph_info:
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dma_free_coherent(trans->dev,
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sizeof(*prph_info),
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prph_info,
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trans_pcie->prph_info_dma_addr);
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err_free_prph_scratch:
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dma_free_coherent(trans->dev,
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sizeof(*prph_scratch),
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prph_scratch,
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trans_pcie->prph_scratch_dma_addr);
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return ret;
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}
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void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
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