forked from luck/tmp_suning_uos_patched
gpio: Update documentation
Strictify the language a bit, move things around, make proper headings, mention pull-up and pull-down, expand unreadable acronyms etc. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
7358a821f0
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0fbee1df20
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@ -1,10 +1,8 @@
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================================
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GPIO Descriptor Driver Interface
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================================
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=====================
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GPIO Driver Interface
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=====================
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This document serves as a guide for GPIO chip drivers writers. Note that it
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describes the new descriptor-based interface. For a description of the
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deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
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This document serves as a guide for writers of GPIO chip drivers.
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Each GPIO controller driver needs to include the following header, which defines
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the structures used to define a GPIO driver:
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@ -15,32 +13,49 @@ the structures used to define a GPIO driver:
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Internal Representation of GPIOs
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================================
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Inside a GPIO driver, individual GPIOs are identified by their hardware number,
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which is a unique number between 0 and n, n being the number of GPIOs managed by
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the chip. This number is purely internal: the hardware number of a particular
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GPIO descriptor is never made visible outside of the driver.
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A GPIO chip handles one or more GPIO lines. To be considered a GPIO chip, the
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lines must conform to the definition: General Purpose Input/Output. If the
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line is not general purpose, it is not GPIO and should not be handled by a
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GPIO chip. The use case is the indicative: certain lines in a system may be
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called GPIO but serve a very particular purpose thus not meeting the criteria
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of a general purpose I/O. On the other hand a LED driver line may be used as a
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GPIO and should therefore still be handled by a GPIO chip driver.
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On top of this internal number, each GPIO also need to have a global number in
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the integer GPIO namespace so that it can be used with the legacy GPIO
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Inside a GPIO driver, individual GPIO lines are identified by their hardware
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number, sometime also referred to as ``offset``, which is a unique number
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between 0 and n-1, n being the number of GPIOs managed by the chip.
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The hardware GPIO number should be something intuitive to the hardware, for
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example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
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lines are handled by one bit per line in a 32-bit register, it makes sense to
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use hardware offsets 0..31 for these, corresponding to bits 0..31 in the
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register.
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This number is purely internal: the hardware number of a particular GPIO
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line is never made visible outside of the driver.
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On top of this internal number, each GPIO line also needs to have a global
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number in the integer GPIO namespace so that it can be used with the legacy GPIO
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interface. Each chip must thus have a "base" number (which can be automatically
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assigned), and for each GPIO the global number will be (base + hardware number).
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Although the integer representation is considered deprecated, it still has many
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users and thus needs to be maintained.
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assigned), and for each GPIO line the global number will be (base + hardware
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number). Although the integer representation is considered deprecated, it still
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has many users and thus needs to be maintained.
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So for example one platform could use numbers 32-159 for GPIOs, with a
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So for example one platform could use global numbers 32-159 for GPIOs, with a
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controller defining 128 GPIOs at a "base" of 32 ; while another platform uses
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numbers 0..63 with one set of GPIO controllers, 64-79 with another type of GPIO
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controller, and on one particular board 80-95 with an FPGA. The numbers need not
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be contiguous; either of those platforms could also use numbers 2000-2063 to
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identify GPIOs in a bank of I2C GPIO expanders.
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global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
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of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
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numbers need not be contiguous; either of those platforms could also use numbers
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2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
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Controller Drivers: gpio_chip
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=============================
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In the gpiolib framework each GPIO controller is packaged as a "struct
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gpio_chip" (see linux/gpio/driver.h for its complete definition) with members
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common to each controller of that type:
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gpio_chip" (see <linux/gpio/driver.h> for its complete definition) with members
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common to each controller of that type, these should be assigned by the
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driver code:
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- methods to establish GPIO line direction
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- methods used to access GPIO line values
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@ -48,12 +63,12 @@ common to each controller of that type:
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- method to return the IRQ number associated to a given GPIO line
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- flag saying whether calls to its methods may sleep
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- optional line names array to identify lines
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- optional debugfs dump method (showing extra state like pullup config)
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- optional debugfs dump method (showing extra state information)
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- optional base number (will be automatically assigned if omitted)
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- optional label for diagnostics and GPIO chip mapping using platform data
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The code implementing a gpio_chip should support multiple instances of the
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controller, possibly using the driver model. That code will configure each
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controller, preferably using the driver model. That code will configure each
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gpio_chip and issue ``gpiochip_add[_data]()`` or ``devm_gpiochip_add_data()``.
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Removing a GPIO controller should be rare; use ``[devm_]gpiochip_remove()``
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when it is unavoidable.
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@ -62,24 +77,28 @@ Often a gpio_chip is part of an instance-specific structure with states not
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exposed by the GPIO interfaces, such as addressing, power management, and more.
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Chips such as audio codecs will have complex non-GPIO states.
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Any debugfs dump method should normally ignore signals which haven't been
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requested as GPIOs. They can use gpiochip_is_requested(), which returns either
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NULL or the label associated with that GPIO when it was requested.
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Any debugfs dump method should normally ignore lines which haven't been
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requested. They can use gpiochip_is_requested(), which returns either
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NULL or the label associated with that GPIO line when it was requested.
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RT_FULL: the GPIO driver should not use spinlock_t or any sleepable APIs
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(like PM runtime) in its gpio_chip implementation (.get/.set and direction
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control callbacks) if it is expected to call GPIO APIs from atomic context
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on -RT (inside hard IRQ handlers and similar contexts). Normally this should
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not be required.
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Realtime considerations: the GPIO driver should not use spinlock_t or any
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sleepable APIs (like PM runtime) in its gpio_chip implementation (.get/.set
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and direction control callbacks) if it is expected to call GPIO APIs from
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atomic context on realtime kernels (inside hard IRQ handlers and similar
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contexts). Normally this should not be required.
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GPIO electrical configuration
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-----------------------------
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GPIOs can be configured for several electrical modes of operation by using the
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.set_config() callback. Currently this API supports setting debouncing and
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single-ended modes (open drain/open source). These settings are described
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below.
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GPIO lines can be configured for several electrical modes of operation by using
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the .set_config() callback. Currently this API supports setting:
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- Debouncing
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- Single-ended modes (open drain/open source)
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- Pull up and pull down resistor enablement
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These settings are described below.
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The .set_config() callback uses the same enumerators and configuration
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semantics as the generic pin control drivers. This is not a coincidence: it is
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@ -94,8 +113,8 @@ description needs to provide "GPIO ranges" mapping the GPIO line offsets to pin
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numbers on the pin controller so they can properly cross-reference each other.
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GPIOs with debounce support
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---------------------------
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GPIO lines with debounce support
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--------------------------------
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Debouncing is a configuration set to a pin indicating that it is connected to
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a mechanical switch or button, or similar that may bounce. Bouncing means the
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@ -111,8 +130,8 @@ a certain number of milliseconds for debouncing, or just "on/off" if that time
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is not configurable.
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GPIOs with open drain/source support
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------------------------------------
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GPIO lines with open drain/source support
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-----------------------------------------
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Open drain (CMOS) or open collector (TTL) means the line is not actively driven
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high: instead you provide the drain/collector as output, so when the transistor
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@ -132,13 +151,13 @@ This configuration is normally used as a way to achieve one of two things:
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- Level-shifting: to reach a logical level higher than that of the silicon
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where the output resides.
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- inverse wire-OR on an I/O line, for example a GPIO line, making it possible
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- Inverse wire-OR on an I/O line, for example a GPIO line, making it possible
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for any driving stage on the line to drive it low even if any other output
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to the same line is simultaneously driving it high. A special case of this
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is driving the SCL and SDA lines of an I2C bus, which is by definition a
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wire-OR bus.
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Both usecases require that the line be equipped with a pull-up resistor. This
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Both use cases require that the line be equipped with a pull-up resistor. This
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resistor will make the line tend to high level unless one of the transistors on
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the rail actively pulls it down.
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@ -208,27 +227,91 @@ For open source configuration the same principle is used, just that instead
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of actively driving the line low, it is set to input.
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GPIO lines with pull up/down resistor support
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---------------------------------------------
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A GPIO line can support pull-up/down using the .set_config() callback. This
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means that a pull up or pull-down resistor is available on the output of the
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GPIO line, and this resistor is software controlled.
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In discrete designs, a pull-up or pull-down resistor is simply soldered on
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the circuit board. This is not something we deal or model in software. The
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most you will think about these lines is that they will very likely be
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configured as open drain or open source (see the section above).
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The .set_config() callback can only turn pull up or down on and off, and will
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no have any semantic knowledge about the resistance used. It will only say
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switch a bit in a register enabling or disabling pull-up or pull-down.
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If the GPIO line supports shunting in different resistance values for the
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pull-up or pull-down resistor, the GPIO chip callback .set_config() will not
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suffice. For these complex use cases, a combined GPIO chip and pin controller
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need to be implemented, as the pin config interface of a pin controller
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supports more versatile control over electrical properties and can handle
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different pull-up or pull-down resistance values.
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GPIO drivers providing IRQs
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---------------------------
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===========================
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It is custom that GPIO drivers (GPIO chips) are also providing interrupts,
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most often cascaded off a parent interrupt controller, and in some special
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cases the GPIO logic is melded with a SoC's primary interrupt controller.
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The IRQ portions of the GPIO block are implemented using an irqchip, using
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The IRQ portions of the GPIO block are implemented using an irq_chip, using
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the header <linux/irq.h>. So basically such a driver is utilizing two sub-
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systems simultaneously: gpio and irq.
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RT_FULL: a realtime compliant GPIO driver should not use spinlock_t or any
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sleepable APIs (like PM runtime) as part of its irq_chip implementation.
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It is legal for any IRQ consumer to request an IRQ from any irqchip even if it
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is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
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irq_chip are orthogonal, and offering their services independent of each
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other.
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* spinlock_t should be replaced with raw_spinlock_t [1].
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* If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
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gpiod_to_irq() is just a convenience function to figure out the IRQ for a
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certain GPIO line and should not be relied upon to have been called before
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the IRQ is used.
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Always prepare the hardware and make it ready for action in respective
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callbacks from the GPIO and irq_chip APIs. Do not rely on gpiod_to_irq() having
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been called first.
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We can divide GPIO irqchips in two broad categories:
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- CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
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interrupt output line, which is triggered by any enabled GPIO line on that
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chip. The interrupt output line will then be routed to an parent interrupt
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controller one level up, in the most simple case the systems primary
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interrupt controller. This is modeled by an irqchip that will inspect bits
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inside the GPIO controller to figure out which line fired it. The irqchip
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part of the driver needs to inspect registers to figure this out and it
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will likely also need to acknowledge that it is handling the interrupt
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by clearing some bit (sometime implicitly, by just reading a status
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register) and it will often need to set up the configuration such as
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edge sensitivity (rising or falling edge, or high/low level interrupt for
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example).
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- HIERARCHICAL INTERRUPT CHIPS: this means that each GPIO line has a dedicated
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irq line to a parent interrupt controller one level up. There is no need
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to inquire the GPIO hardware to figure out which line has figured, but it
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may still be necessary to acknowledge the interrupt and set up the
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configuration such as edge sensitivity.
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Realtime considerations: a realtime compliant GPIO driver should not use
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spinlock_t or any sleepable APIs (like PM runtime) as part of its irqchip
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implementation.
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- spinlock_t should be replaced with raw_spinlock_t [1].
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- If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
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and .irq_bus_unlock() callbacks, as these are the only slowpath callbacks
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on an irqchip. Create the callbacks if needed [2].
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GPIO irqchips usually fall in one of two categories:
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* CHAINED GPIO irqchips: these are usually the type that is embedded on
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Cascaded GPIO irqchips
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----------------------
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Cascaded GPIO irqchips usually fall in one of three categories:
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- CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
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an SoC. This means that there is a fast IRQ flow handler for the GPIOs that
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gets called in a chain from the parent IRQ handler, most typically the
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system interrupt controller. This means that the GPIO irqchip handler will
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@ -245,16 +328,19 @@ GPIO irqchips usually fall in one of two categories:
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struct gpio_chip, as everything happens directly in the callbacks: no
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slow bus traffic like I2C can be used.
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RT_FULL: Note, chained IRQ handlers will not be forced threaded on -RT.
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As result, spinlock_t or any sleepable APIs (like PM runtime) can't be used
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in chained IRQ handler.
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If required (and if it can't be converted to the nested threaded GPIO irqchip)
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a chained IRQ handler can be converted to generic irq handler and this way
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it will be a threaded IRQ handler on -RT and a hard IRQ handler on non-RT
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(for example, see [3]).
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Know W/A: The generic_handle_irq() is expected to be called with IRQ disabled,
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Realtime considerations: Note that chained IRQ handlers will not be forced
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threaded on -RT. As a result, spinlock_t or any sleepable APIs (like PM
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runtime) can't be used in a chained IRQ handler.
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If required (and if it can't be converted to the nested threaded GPIO irqchip,
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see below) a chained IRQ handler can be converted to generic irq handler and
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this way it will become a threaded IRQ handler on -RT and a hard IRQ handler
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on non-RT (for example, see [3]).
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The generic_handle_irq() is expected to be called with IRQ disabled,
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so the IRQ core will complain if it is called from an IRQ handler which is
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forced to a thread. The "fake?" raw lock can be used to W/A this problem::
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forced to a thread. The "fake?" raw lock can be used to work around this
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problem::
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raw_spinlock_t wa_lock;
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static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
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@ -263,7 +349,7 @@ GPIO irqchips usually fall in one of two categories:
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generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
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raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
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* GENERIC CHAINED GPIO irqchips: these are the same as "CHAINED GPIO irqchips",
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- GENERIC CHAINED GPIO IRQCHIPS: these are the same as "CHAINED GPIO irqchips",
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but chained IRQ handlers are not used. Instead GPIO IRQs dispatching is
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performed by generic IRQ handler which is configured using request_irq().
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The GPIO irqchip will then end up calling something like this sequence in
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@ -273,16 +359,19 @@ GPIO irqchips usually fall in one of two categories:
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for each detected GPIO IRQ
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generic_handle_irq(...);
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RT_FULL: Such kind of handlers will be forced threaded on -RT, as result IRQ
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core will complain that generic_handle_irq() is called with IRQ enabled and
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the same W/A as for "CHAINED GPIO irqchips" can be applied.
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Realtime considerations: this kind of handlers will be forced threaded on -RT,
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and as result the IRQ core will complain that generic_handle_irq() is called
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with IRQ enabled and the same work around as for "CHAINED GPIO irqchips" can
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be applied.
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* NESTED THREADED GPIO irqchips: these are off-chip GPIO expanders and any
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other GPIO irqchip residing on the other side of a sleeping bus. Of course
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such drivers that need slow bus traffic to read out IRQ status and similar,
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traffic which may in turn incur other IRQs to happen, cannot be handled
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in a quick IRQ handler with IRQs disabled. Instead they need to spawn a
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thread and then mask the parent IRQ line until the interrupt is handled
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- NESTED THREADED GPIO IRQCHIPS: these are off-chip GPIO expanders and any
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other GPIO irqchip residing on the other side of a sleeping bus such as I2C
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or SPI.
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Of course such drivers that need slow bus traffic to read out IRQ status and
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similar, traffic which may in turn incur other IRQs to happen, cannot be
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handled in a quick IRQ handler with IRQs disabled. Instead they need to spawn
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a thread and then mask the parent IRQ line until the interrupt is handled
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by the driver. The hallmark of this driver is to call something like
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this in its interrupt handler::
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@ -294,36 +383,46 @@ GPIO irqchips usually fall in one of two categories:
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flag on struct gpio_chip to true, indicating that this chip may sleep
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when accessing the GPIOs.
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These kinds of irqchips are inherently realtime tolerant as they are
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already set up to handle sleeping contexts.
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Infrastructure helpers for GPIO irqchips
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----------------------------------------
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To help out in handling the set-up and management of GPIO irqchips and the
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associated irqdomain and resource allocation callbacks, the gpiolib has
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some helpers that can be enabled by selecting the GPIOLIB_IRQCHIP Kconfig
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symbol:
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* gpiochip_irqchip_add(): adds a chained irqchip to a gpiochip. It will pass
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the struct gpio_chip* for the chip to all IRQ callbacks, so the callbacks
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need to embed the gpio_chip in its state container and obtain a pointer
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to the container using container_of().
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- gpiochip_irqchip_add(): adds a chained cascaded irqchip to a gpiochip. It
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will pass the struct gpio_chip* for the chip to all IRQ callbacks, so the
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callbacks need to embed the gpio_chip in its state container and obtain a
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pointer to the container using container_of().
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(See Documentation/driver-model/design-patterns.txt)
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* gpiochip_irqchip_add_nested(): adds a nested irqchip to a gpiochip.
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- gpiochip_irqchip_add_nested(): adds a nested cascaded irqchip to a gpiochip,
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as discussed above regarding different types of cascaded irqchips. The
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cascaded irq has to be handled by a threaded interrupt handler.
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Apart from that it works exactly like the chained irqchip.
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* gpiochip_set_chained_irqchip(): sets up a chained irq handler for a
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- gpiochip_set_chained_irqchip(): sets up a chained cascaded irq handler for a
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gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler
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data. (Notice handler data, since the irqchip data is likely used by the
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parent irqchip!).
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data. Notice that we pass is as the handler data, since the irqchip data is
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likely used by the parent irqchip.
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* gpiochip_set_nested_irqchip(): sets up a nested irq handler for a
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- gpiochip_set_nested_irqchip(): sets up a nested cascaded irq handler for a
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gpio_chip from a parent IRQ. As the parent IRQ has usually been
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explicitly requested by the driver, this does very little more than
|
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mark all the child IRQs as having the other IRQ as parent.
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If there is a need to exclude certain GPIOs from the IRQ domain, you can
|
||||
set .irq.need_valid_mask of the gpiochip before gpiochip_add_data() is
|
||||
called. This allocates an .irq.valid_mask with as many bits set as there
|
||||
are GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this
|
||||
mask. The mask must be filled in before gpiochip_irqchip_add() or
|
||||
gpiochip_irqchip_add_nested() is called.
|
||||
If there is a need to exclude certain GPIO lines from the IRQ domain handled by
|
||||
these helpers, we can set .irq.need_valid_mask of the gpiochip before
|
||||
[devm_]gpiochip_add_data() is called. This allocates an .irq.valid_mask with as
|
||||
many bits set as there are GPIO lines in the chip, each bit representing line
|
||||
0..n-1. Drivers can exclude GPIO lines by clearing bits from this mask. The mask
|
||||
must be filled in before gpiochip_irqchip_add() or gpiochip_irqchip_add_nested()
|
||||
is called.
|
||||
|
||||
To use the helpers please keep the following in mind:
|
||||
|
||||
|
|
@ -333,33 +432,24 @@ To use the helpers please keep the following in mind:
|
|||
|
||||
- Nominally set all handlers to handle_bad_irq() in the setup call and pass
|
||||
handle_bad_irq() as flow handler parameter in gpiochip_irqchip_add() if it is
|
||||
expected for GPIO driver that irqchip .set_type() callback have to be called
|
||||
before using/enabling GPIO IRQ. Then set the handler to handle_level_irq()
|
||||
and/or handle_edge_irq() in the irqchip .set_type() callback depending on
|
||||
what your controller supports.
|
||||
|
||||
It is legal for any IRQ consumer to request an IRQ from any irqchip no matter
|
||||
if that is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
|
||||
irq_chip are orthogonal, and offering their services independent of each
|
||||
other.
|
||||
|
||||
gpiod_to_irq() is just a convenience function to figure out the IRQ for a
|
||||
certain GPIO line and should not be relied upon to have been called before
|
||||
the IRQ is used.
|
||||
|
||||
So always prepare the hardware and make it ready for action in respective
|
||||
callbacks from the GPIO and irqchip APIs. Do not rely on gpiod_to_irq() having
|
||||
been called first.
|
||||
|
||||
This orthogonality leads to ambiguities that we need to solve: if there is
|
||||
competition inside the subsystem which side is using the resource (a certain
|
||||
GPIO line and register for example) it needs to deny certain operations and
|
||||
keep track of usage inside of the gpiolib subsystem. This is why the API
|
||||
below exists.
|
||||
expected for GPIO driver that irqchip .set_type() callback will be called
|
||||
before using/enabling each GPIO IRQ. Then set the handler to
|
||||
handle_level_irq() and/or handle_edge_irq() in the irqchip .set_type()
|
||||
callback depending on what your controller supports and what is requested
|
||||
by the consumer.
|
||||
|
||||
|
||||
Locking IRQ usage
|
||||
-----------------
|
||||
|
||||
Since GPIO and irq_chip are orthogonal, we can get conflicts between different
|
||||
use cases. For example a GPIO line used for IRQs should be an input line,
|
||||
it does not make sense to fire interrupts on an output GPIO.
|
||||
|
||||
If there is competition inside the subsystem which side is using the
|
||||
resource (a certain GPIO line and register for example) it needs to deny
|
||||
certain operations and keep track of usage inside of the gpiolib subsystem.
|
||||
|
||||
Input GPIOs can be used as IRQ signals. When this happens, a driver is requested
|
||||
to mark the GPIO as being used as an IRQ::
|
||||
|
||||
|
|
@ -380,9 +470,15 @@ assigned.
|
|||
|
||||
Disabling and enabling IRQs
|
||||
---------------------------
|
||||
|
||||
In some (fringe) use cases, a driver may be using a GPIO line as input for IRQs,
|
||||
but occasionally switch that line over to drive output and then back to being
|
||||
an input with interrupts again. This happens on things like CEC (Consumer
|
||||
Electronics Control).
|
||||
|
||||
When a GPIO is used as an IRQ signal, then gpiolib also needs to know if
|
||||
the IRQ is enabled or disabled. In order to inform gpiolib about this,
|
||||
a driver should call::
|
||||
the irqchip driver should call::
|
||||
|
||||
void gpiochip_disable_irq(struct gpio_chip *chip, unsigned int offset)
|
||||
|
||||
|
|
@ -398,40 +494,45 @@ irqchip.
|
|||
When using the gpiolib irqchip helpers, these callbacks are automatically
|
||||
assigned.
|
||||
|
||||
|
||||
Real-Time compliance for GPIO IRQ chips
|
||||
---------------------------------------
|
||||
|
||||
Any provider of irqchips needs to be carefully tailored to support Real Time
|
||||
Any provider of irqchips needs to be carefully tailored to support Real-Time
|
||||
preemption. It is desirable that all irqchips in the GPIO subsystem keep this
|
||||
in mind and do the proper testing to assure they are real time-enabled.
|
||||
So, pay attention on above " RT_FULL:" notes, please.
|
||||
The following is a checklist to follow when preparing a driver for real
|
||||
time-compliance:
|
||||
|
||||
- ensure spinlock_t is not used as part irq_chip implementation;
|
||||
- ensure that sleepable APIs are not used as part irq_chip implementation.
|
||||
So, pay attention on above realtime considerations in the documentation.
|
||||
|
||||
The following is a checklist to follow when preparing a driver for real-time
|
||||
compliance:
|
||||
|
||||
- ensure spinlock_t is not used as part irq_chip implementation
|
||||
- ensure that sleepable APIs are not used as part irq_chip implementation
|
||||
If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
|
||||
and .irq_bus_unlock() callbacks;
|
||||
and .irq_bus_unlock() callbacks
|
||||
- Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
|
||||
from chained IRQ handler;
|
||||
from the chained IRQ handler
|
||||
- Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
|
||||
apply corresponding W/A;
|
||||
- Chained GPIO irqchips: get rid of chained IRQ handler and use generic irq
|
||||
handler if possible :)
|
||||
- regmap_mmio: Sry, but you are in trouble :( if MMIO regmap is used as for
|
||||
GPIO IRQ chip implementation;
|
||||
- Test your driver with the appropriate in-kernel real time test cases for both
|
||||
level and edge IRQs.
|
||||
apply corresponding work-around
|
||||
- Chained GPIO irqchips: get rid of the chained IRQ handler and use generic irq
|
||||
handler if possible
|
||||
- regmap_mmio: it is possible to disable internal locking in regmap by setting
|
||||
.disable_locking and handling the locking in the GPIO driver
|
||||
- Test your driver with the appropriate in-kernel real-time test cases for both
|
||||
level and edge IRQs
|
||||
|
||||
* [1] http://www.spinics.net/lists/linux-omap/msg120425.html
|
||||
* [2] https://lkml.org/lkml/2015/9/25/494
|
||||
* [3] https://lkml.org/lkml/2015/9/25/495
|
||||
|
||||
|
||||
Requesting self-owned GPIO pins
|
||||
-------------------------------
|
||||
===============================
|
||||
|
||||
Sometimes it is useful to allow a GPIO chip driver to request its own GPIO
|
||||
descriptors through the gpiolib API. Using gpio_request() for this purpose
|
||||
does not help since it pins the module to the kernel forever (it calls
|
||||
try_module_get()). A GPIO driver can use the following functions instead
|
||||
to request and free descriptors without being pinned to the kernel forever::
|
||||
descriptors through the gpiolib API. A GPIO driver can use the following
|
||||
functions to request and free descriptors::
|
||||
|
||||
struct gpio_desc *gpiochip_request_own_desc(struct gpio_desc *desc,
|
||||
u16 hwnum,
|
||||
|
|
@ -446,7 +547,3 @@ gpiochip_free_own_desc().
|
|||
These functions must be used with care since they do not affect module use
|
||||
count. Do not use the functions to request gpio descriptors not owned by the
|
||||
calling driver.
|
||||
|
||||
* [1] http://www.spinics.net/lists/linux-omap/msg120425.html
|
||||
* [2] https://lkml.org/lkml/2015/9/25/494
|
||||
* [3] https://lkml.org/lkml/2015/9/25/495
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user