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MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions

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MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and
BNEZLAC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras 2014-11-26 15:03:54 +00:00
parent c893ce38b2
commit 10d962d534
3 changed files with 7 additions and 2 deletions
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2
arch/mips/include/uapi/asm/inst.h
View File

@ -25,7 +25,7 @@ enum major_op {
andi_op, ori_op, xori_op, lui_op,
cop0_op, cop1_op, cop2_op, cop1x_op,
beql_op, bnel_op, blezl_op, bgtzl_op,
daddi_op, daddiu_op, ldl_op, ldr_op,
daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
spec2_op, jalx_op, mdmx_op, spec3_op,
lb_op, lh_op, lwl_op, lw_op,
lbu_op, lhu_op, lwr_op, lwu_op,

6
arch/mips/kernel/branch.c
View File

@ -791,12 +791,16 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
break;
#endif
case cbcond0_op:
case cbcond1_op:
/* Only valid for MIPS R6 */
if (!cpu_has_mips_r6) {
ret = -SIGILL;
break;
}
/* Compact branches: bovc, beqc, beqzalc */
/*
* Compact branches:
* bovc, beqc, beqzalc, bnvc, bnec, bnezlac
*/
if (insn.i_format.rt && !insn.i_format.rs)
regs->regs[31] = epc + 4;
regs->cp0_epc += 8;

1
arch/mips/math-emu/cp1emu.c
View File

@ -624,6 +624,7 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
dec_insn.next_pc_inc;
return 1;
case cbcond0_op:
case cbcond1_op:
if (!cpu_has_mips_r6)
break;
if (insn.i_format.rt && !insn.i_format.rs)