forked from luck/tmp_suning_uos_patched
EDAC, altera: Add Arria10 ECC memory init functions
In preparation for additional memory module ECCs, add the memory initialization functions and helpers. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1466603939-7526-7-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Thor Thayer
Borislav Petkov
parent
f103ad1556
commit
1166fde93d
@ -19,6 +19,7 @@
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#include <asm/cacheflush.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/edac.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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@ -874,6 +875,197 @@ static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
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return IRQ_NONE;
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}
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/******************* Arria10 Memory Buffer Functions *********************/
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static inline int a10_get_irq_mask(struct device_node *np)
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{
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int irq;
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const u32 *handle = of_get_property(np, "interrupts", NULL);
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if (!handle)
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return -ENODEV;
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irq = be32_to_cpup(handle);
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return irq;
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}
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static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr);
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value |= bit_mask;
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writel(value, ioaddr);
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}
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static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr);
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value &= ~bit_mask;
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writel(value, ioaddr);
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}
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static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr);
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return (value & bit_mask) ? 1 : 0;
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}
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/*
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* This function uses the memory initialization block in the Arria10 ECC
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* controller to initialize/clear the entire memory data and ECC data.
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*/
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static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
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{
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int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
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u32 init_mask, stat_mask, clear_mask;
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int ret = 0;
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if (port) {
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init_mask = ALTR_A10_ECC_INITB;
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stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
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clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
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} else {
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init_mask = ALTR_A10_ECC_INITA;
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stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
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clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
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}
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ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
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while (limit--) {
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if (ecc_test_bits(stat_mask,
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(ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
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break;
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udelay(1);
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}
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if (limit < 0)
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ret = -EBUSY;
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/* Clear any pending ECC interrupts */
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writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
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return ret;
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}
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static __init int __maybe_unused
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altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
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u32 ecc_ctrl_en_mask, bool dual_port)
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{
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int ret = 0;
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void __iomem *ecc_block_base;
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struct regmap *ecc_mgr_map;
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char *ecc_name;
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struct device_node *np_eccmgr;
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ecc_name = (char *)np->name;
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/* Get the ECC Manager - parent of the device EDACs */
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np_eccmgr = of_get_parent(np);
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ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
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"altr,sysmgr-syscon");
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of_node_put(np_eccmgr);
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if (IS_ERR(ecc_mgr_map)) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to get syscon altr,sysmgr-syscon\n");
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return -ENODEV;
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}
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/* Map the ECC Block */
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ecc_block_base = of_iomap(np, 0);
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if (!ecc_block_base) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"Unable to map %s ECC block\n", ecc_name);
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return -ENODEV;
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}
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/* Disable ECC */
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regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
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writel(ALTR_A10_ECC_SERRINTEN,
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(ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
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ecc_clear_bits(ecc_ctrl_en_mask,
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(ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
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/* Ensure all writes complete */
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wmb();
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/* Use HW initialization block to initialize memory for ECC */
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ret = altr_init_memory_port(ecc_block_base, 0);
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if (ret) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"ECC: cannot init %s PORTA memory\n", ecc_name);
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goto out;
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}
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if (dual_port) {
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ret = altr_init_memory_port(ecc_block_base, 1);
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if (ret) {
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edac_printk(KERN_ERR, EDAC_DEVICE,
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"ECC: cannot init %s PORTB memory\n",
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ecc_name);
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goto out;
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}
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}
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/* Interrupt mode set to every SBERR */
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regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
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ALTR_A10_ECC_INTMODE);
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/* Enable ECC */
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ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
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ALTR_A10_ECC_CTRL_OFST));
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writel(ALTR_A10_ECC_SERRINTEN,
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(ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
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regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
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/* Ensure all writes complete */
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wmb();
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out:
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iounmap(ecc_block_base);
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return ret;
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}
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static int validate_parent_available(struct device_node *np);
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static const struct of_device_id altr_edac_a10_device_of_match[];
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static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
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{
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int irq;
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struct device_node *child, *np = of_find_compatible_node(NULL, NULL,
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"altr,socfpga-a10-ecc-manager");
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if (!np) {
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edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
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return -ENODEV;
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}
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for_each_child_of_node(np, child) {
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const struct of_device_id *pdev_id;
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const struct edac_device_prv_data *prv;
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if (!of_device_is_available(child))
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continue;
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if (!of_device_is_compatible(child, compat))
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continue;
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if (validate_parent_available(child))
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continue;
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irq = a10_get_irq_mask(child);
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if (irq < 0)
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continue;
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/* Get matching node and check for valid result */
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pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
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if (IS_ERR_OR_NULL(pdev_id))
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continue;
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/* Validate private data pointer before dereferencing */
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prv = pdev_id->data;
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if (!prv)
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continue;
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altr_init_a10_ecc_block(child, BIT(irq),
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prv->ecc_enable_mask, 0);
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}
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of_node_put(np);
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return 0;
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}
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/*********************** OCRAM EDAC Device Functions *********************/
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#ifdef CONFIG_EDAC_ALTERA_OCRAM
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@ -230,8 +230,13 @@ struct altr_sdram_mc_data {
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#define ALTR_A10_ECC_INITCOMPLETEB BIT(8)
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#define ALTR_A10_ECC_ERRINTEN_OFST 0x10
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#define ALTR_A10_ECC_ERRINTENS_OFST 0x14
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#define ALTR_A10_ECC_ERRINTENR_OFST 0x18
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#define ALTR_A10_ECC_SERRINTEN BIT(0)
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#define ALTR_A10_ECC_INTMODE_OFST 0x1C
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#define ALTR_A10_ECC_INTMODE BIT(0)
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#define ALTR_A10_ECC_INTSTAT_OFST 0x20
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#define ALTR_A10_ECC_SERRPENA BIT(0)
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#define ALTR_A10_ECC_DERRPENA BIT(8)
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@ -280,6 +285,9 @@ struct altr_sdram_mc_data {
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/* Arria 10 OCRAM ECC Management Group Defines */
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#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
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/* A10 ECC Controller memory initialization timeout */
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#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
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struct altr_edac_device_dev;
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struct edac_device_prv_data {
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