forked from luck/tmp_suning_uos_patched
[SCSI] qla2xxx: Export TLV data on supported ISPs.
Firmware currently provides PB and PGF TLVs. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
This commit is contained in:
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ce0423f4a2
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11bbc1d896
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@ -744,6 +744,57 @@ static struct bin_attribute sysfs_xgmac_stats_attr = {
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.read = qla2x00_sysfs_read_xgmac_stats,
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};
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static ssize_t
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qla2x00_sysfs_read_dcbx_tlv(struct kobject *kobj,
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struct bin_attribute *bin_attr,
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char *buf, loff_t off, size_t count)
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{
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struct scsi_qla_host *vha = shost_priv(dev_to_shost(container_of(kobj,
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struct device, kobj)));
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struct qla_hw_data *ha = vha->hw;
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int rval;
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uint16_t actual_size;
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if (!capable(CAP_SYS_ADMIN) || off != 0 || count > DCBX_TLV_DATA_SIZE)
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return 0;
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if (ha->dcbx_tlv)
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goto do_read;
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ha->dcbx_tlv = dma_alloc_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
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&ha->dcbx_tlv_dma, GFP_KERNEL);
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if (!ha->dcbx_tlv) {
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qla_printk(KERN_WARNING, ha,
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"Unable to allocate memory for DCBX TLV read-data.\n");
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return 0;
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}
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do_read:
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actual_size = 0;
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memset(ha->dcbx_tlv, 0, DCBX_TLV_DATA_SIZE);
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rval = qla2x00_get_dcbx_params(vha, ha->dcbx_tlv_dma,
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DCBX_TLV_DATA_SIZE);
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if (rval != QLA_SUCCESS) {
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qla_printk(KERN_WARNING, ha,
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"Unable to read DCBX TLV data (%x).\n", rval);
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count = 0;
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}
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memcpy(buf, ha->dcbx_tlv, count);
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return count;
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}
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static struct bin_attribute sysfs_dcbx_tlv_attr = {
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.attr = {
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.name = "dcbx_tlv",
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.mode = S_IRUSR,
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},
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.size = 0,
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.read = qla2x00_sysfs_read_dcbx_tlv,
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};
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static struct sysfs_entry {
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char *name;
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struct bin_attribute *attr;
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@ -759,6 +810,7 @@ static struct sysfs_entry {
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{ "edc", &sysfs_edc_attr, 2 },
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{ "edc_status", &sysfs_edc_status_attr, 2 },
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{ "xgmac_stats", &sysfs_xgmac_stats_attr, 3 },
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{ "dcbx_tlv", &sysfs_dcbx_tlv_attr, 3 },
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{ NULL },
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};
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@ -2401,6 +2401,10 @@ struct qla_hw_data {
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void *xgmac_data;
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dma_addr_t xgmac_data_dma;
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#define DCBX_TLV_DATA_SIZE PAGE_SIZE
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void *dcbx_tlv;
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dma_addr_t dcbx_tlv_dma;
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struct task_struct *dpc_thread;
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uint8_t dpc_active; /* DPC routine is active */
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@ -1406,6 +1406,7 @@ struct access_chip_rsp_84xx {
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#define MBC_RESTART_MPI_FW 0x3d
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#define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
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#define MBC_GET_XGMAC_STATS 0x7a
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#define MBC_GET_DCBX_PARAMS 0x51
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/* Flash access control option field bit definitions */
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#define FAC_OPT_FORCE_SEMAPHORE BIT_15
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@ -296,6 +296,9 @@ qla81xx_fac_erase_sector(scsi_qla_host_t *, uint32_t, uint32_t);
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extern int
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qla2x00_get_xgmac_stats(scsi_qla_host_t *, dma_addr_t, uint16_t, uint16_t *);
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extern int
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qla2x00_get_dcbx_params(scsi_qla_host_t *, dma_addr_t, uint16_t);
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/*
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* Global Function Prototypes in qla_isr.c source file.
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*/
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@ -3500,3 +3500,40 @@ qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
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return rval;
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}
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int
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qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
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uint16_t size)
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{
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int rval;
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mbx_cmd_t mc;
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mbx_cmd_t *mcp = &mc;
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if (!IS_QLA81XX(vha->hw))
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return QLA_FUNCTION_FAILED;
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DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no));
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mcp->mb[0] = MBC_GET_DCBX_PARAMS;
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mcp->mb[1] = 0;
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mcp->mb[2] = MSW(tlv_dma);
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mcp->mb[3] = LSW(tlv_dma);
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mcp->mb[6] = MSW(MSD(tlv_dma));
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mcp->mb[7] = LSW(MSD(tlv_dma));
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mcp->mb[8] = size;
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mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
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mcp->in_mb = MBX_2|MBX_1|MBX_0;
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mcp->tov = MBX_TOV_SECONDS;
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mcp->flags = 0;
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rval = qla2x00_mailbox_command(vha, mcp);
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if (rval != QLA_SUCCESS) {
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DEBUG2_3_11(printk("%s(%ld): failed=%x mb[0]=0x%x "
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"mb[1]=0x%x mb[2]=0x%x.\n", __func__, vha->host_no, rval,
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mcp->mb[0], mcp->mb[1], mcp->mb[2]));
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} else {
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DEBUG11(printk("%s(%ld): done.\n", __func__, vha->host_no));
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}
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return rval;
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}
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@ -2434,6 +2434,10 @@ qla2x00_mem_free(struct qla_hw_data *ha)
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vfree(ha->fw_dump);
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}
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if (ha->dcbx_tlv)
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dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
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ha->dcbx_tlv, ha->dcbx_tlv_dma);
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if (ha->xgmac_data)
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dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
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ha->xgmac_data, ha->xgmac_data_dma);
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