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ARM: VIC: remove non MULTI_IRQ_HANDLER support

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Now that all platforms are converted to MULTI_IRQ_HANDLER, remove the
legacy support.

Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
This commit is contained in:
Jamie Iles 2011-11-03 17:32:39 +00:00 committed by Marc Zyngier
parent c05012ce9a
commit 11f1c5de7b
4 changed files with 1 additions and 70 deletions
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11
arch/arm/Kconfig
View File

@ -294,7 +294,6 @@ config ARCH_VERSATILE
select PLAT_VERSATILE_CLCD
select PLAT_VERSATILE_FPGA_IRQ
select ARM_TIMER_SP804
select MULTI_IRQ_HANDLER
help
This enables support for ARM Ltd Versatile board.
@ -410,7 +409,6 @@ config ARCH_EP93XX
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
select MULTI_IRQ_HANDLER
help
This enables support for the Cirrus EP93xx series of CPUs.
@ -452,7 +450,6 @@ config ARCH_NETX
select CPU_ARM926T
select ARM_VIC
select GENERIC_CLOCKEVENTS
select MULTI_IRQ_HANDLER
help
This enables support for systems based on the Hilscher NetX Soc
@ -652,7 +649,6 @@ config ARCH_PICOXCELL
select GENERIC_GPIO
select HAVE_SCHED_CLOCK
select HAVE_TCM
select MULTI_IRQ_HANDLER
select NO_IOPORT
select USE_OF
help
@ -788,7 +784,6 @@ config ARCH_S3C64XX
select SAMSUNG_GPIOLIB_4BIT
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select MULTI_IRQ_HANDLER
help
Samsung S3C64XX series based systems
@ -804,7 +799,6 @@ config ARCH_S5P64X0
select HAVE_SCHED_CLOCK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select MULTI_IRQ_HANDLER
help
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
@ -820,7 +814,6 @@ config ARCH_S5PC100
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select MULTI_IRQ_HANDLER
help
Samsung S5PC100 series based systems
@ -841,7 +834,6 @@ config ARCH_S5PV210
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select NEED_MACH_MEMORY_H
select MULTI_IRQ_HANDLER
help
Samsung S5PV210/S5PC110 series based systems
@ -901,7 +893,6 @@ config ARCH_U300
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select NEED_MACH_MEMORY_H
select MULTI_IRQ_HANDLER
help
Support for ST-Ericsson U300 series mobile platforms.
@ -924,7 +915,6 @@ config ARCH_NOMADIK
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select MULTI_IRQ_HANDLER
help
Support for the Nomadik platform by ST-Ericsson
@ -961,7 +951,6 @@ config PLAT_SPEAR
select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select MULTI_IRQ_HANDLER
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).

1
arch/arm/common/Kconfig
View File

@ -8,6 +8,7 @@ config GIC_NON_BANKED
config ARM_VIC
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
bool
config ARM_VIC_NR

2
arch/arm/common/vic.c
View File

@ -430,7 +430,6 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
}
#endif /* CONFIG OF */
#ifdef CONFIG_MULTI_IRQ_HANDLER
/*
* Handle each interrupt in a single VIC. Returns non-zero if we've
* handled at least one interrupt. This does a single read of the
@ -465,4 +464,3 @@ asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
handled |= handle_one_vic(&vic_devices[i], regs);
} while (handled);
}
#endif /* CONFIG_MULTI_IRQ_HANDLER */

57
arch/arm/include/asm/entry-macro-vic2.S
View File

@ -1,57 +0,0 @@
/* arch/arm/include/asm/entry-macro-vic2.S
*
* Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Low-level IRQ helper macros for a device with two VICs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/* This should be included from <mach/entry-macro.S> with the necessary
* defines for virtual addresses and IRQ bases for the two vics.
*
* The code needs the following defined:
* IRQ_VIC0_BASE IRQ number of VIC0's first IRQ
* IRQ_VIC1_BASE IRQ number of VIC1's first IRQ
* VA_VIC0 Virtual address of VIC0
* VA_VIC1 Virtual address of VIC1
*
* Note, code assumes VIC0's virtual address is an ARM immediate constant
* away from VIC1.
*/
#include <asm/hardware/vic.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =VA_VIC0
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check the vic0
mov \irqnr, #IRQ_VIC0_BASE + 31
ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
teq \irqstat, #0
@ otherwise try vic1
addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
addeq \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm