forked from luck/tmp_suning_uos_patched
Merge tag 'arm-soc/for-3.19/brcmstb-drivers' of https://github.com/brcm/linux into next/drivers
This pull request contains the following changes to the Broadcom GISB bus arbiter from Kevin Cernekee: - Extend brcmstb GISB bus driver to work on MIPS (currently ARM-only) and support 65nm and 40nm MIPS-based chips such as: BCM7038, BCM7400 and BCM7435 * tag 'arm-soc/for-3.19/brcmstb-drivers' of https://github.com/brcm/linux: bus: brcmstb_gisb: Add register offset tables for older chips bus: brcmstb_gisb: Look up register offsets in a table bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses bus: brcmstb_gisb: Make the driver buildable on MIPS Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
136a713d80
@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller
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Required properties:
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- compatible: should be "brcm,gisb-arb"
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- compatible:
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"brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
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"brcm,bcm7435-gisb-arb" for newer 40nm chips
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"brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
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"brcm,bcm7038-gisb-arb" for 130nm chips
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- reg: specifies the base physical address and size of the registers
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this arbiter gets interrupt line from
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@ -6,7 +6,7 @@ menu "Bus devices"
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config BRCMSTB_GISB_ARB
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bool "Broadcom STB GISB bus arbiter"
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depends on ARM
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depends on ARM || MIPS
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help
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Driver for the Broadcom Set Top Box System-on-a-chip internal bus
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arbiter. This driver provides timeout and target abort error handling
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@ -24,26 +24,72 @@
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#include <linux/of.h>
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#include <linux/bitops.h>
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#ifdef CONFIG_ARM
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#include <asm/bug.h>
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#include <asm/signal.h>
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#endif
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#define ARB_TIMER 0x008
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#define ARB_ERR_CAP_CLR 0x7e4
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#define ARB_ERR_CAP_CLEAR (1 << 0)
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#define ARB_ERR_CAP_HI_ADDR 0x7e8
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#define ARB_ERR_CAP_ADDR 0x7ec
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#define ARB_ERR_CAP_DATA 0x7f0
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#define ARB_ERR_CAP_STATUS 0x7f4
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#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
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#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
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#define ARB_ERR_CAP_STATUS_BS_SHIFT (1 << 2)
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#define ARB_ERR_CAP_STATUS_BS_MASK 0x3c
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#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
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#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
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#define ARB_ERR_CAP_MASTER 0x7f8
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enum {
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ARB_TIMER,
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ARB_ERR_CAP_CLR,
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ARB_ERR_CAP_HI_ADDR,
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ARB_ERR_CAP_ADDR,
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ARB_ERR_CAP_DATA,
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ARB_ERR_CAP_STATUS,
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ARB_ERR_CAP_MASTER,
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};
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static const int gisb_offsets_bcm7038[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_ERR_CAP_CLR] = 0x0c4,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x0c8,
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[ARB_ERR_CAP_DATA] = 0x0cc,
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[ARB_ERR_CAP_STATUS] = 0x0d0,
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[ARB_ERR_CAP_MASTER] = -1,
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};
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static const int gisb_offsets_bcm7400[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_ERR_CAP_CLR] = 0x0c8,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x0cc,
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[ARB_ERR_CAP_DATA] = 0x0d0,
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[ARB_ERR_CAP_STATUS] = 0x0d4,
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[ARB_ERR_CAP_MASTER] = 0x0d8,
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};
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static const int gisb_offsets_bcm7435[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_ERR_CAP_CLR] = 0x168,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x16c,
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[ARB_ERR_CAP_DATA] = 0x170,
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[ARB_ERR_CAP_STATUS] = 0x174,
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[ARB_ERR_CAP_MASTER] = 0x178,
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};
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static const int gisb_offsets_bcm7445[] = {
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[ARB_TIMER] = 0x008,
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[ARB_ERR_CAP_CLR] = 0x7e4,
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[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
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[ARB_ERR_CAP_ADDR] = 0x7ec,
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[ARB_ERR_CAP_DATA] = 0x7f0,
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[ARB_ERR_CAP_STATUS] = 0x7f4,
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[ARB_ERR_CAP_MASTER] = 0x7f8,
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};
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struct brcmstb_gisb_arb_device {
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void __iomem *base;
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const int *gisb_offsets;
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struct mutex lock;
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struct list_head next;
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u32 valid_mask;
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@ -52,6 +98,26 @@ struct brcmstb_gisb_arb_device {
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static LIST_HEAD(brcmstb_gisb_arb_device_list);
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static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
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{
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int offset = gdev->gisb_offsets[reg];
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/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
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if (offset == -1)
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return 1;
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return ioread32(gdev->base + offset);
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}
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static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
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{
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int offset = gdev->gisb_offsets[reg];
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if (offset == -1)
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return;
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iowrite32(val, gdev->base + reg);
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}
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static ssize_t gisb_arb_get_timeout(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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@ -61,7 +127,7 @@ static ssize_t gisb_arb_get_timeout(struct device *dev,
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u32 timeout;
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mutex_lock(&gdev->lock);
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timeout = ioread32(gdev->base + ARB_TIMER);
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timeout = gisb_read(gdev, ARB_TIMER);
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mutex_unlock(&gdev->lock);
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return sprintf(buf, "%d", timeout);
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@ -83,7 +149,7 @@ static ssize_t gisb_arb_set_timeout(struct device *dev,
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return -EINVAL;
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mutex_lock(&gdev->lock);
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iowrite32(val, gdev->base + ARB_TIMER);
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gisb_write(gdev, val, ARB_TIMER);
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mutex_unlock(&gdev->lock);
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return count;
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@ -110,18 +176,18 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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const char *m_name;
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char m_fmt[11];
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cap_status = ioread32(gdev->base + ARB_ERR_CAP_STATUS);
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cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
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/* Invalid captured address, bail out */
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if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
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return 1;
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/* Read the address and master */
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arb_addr = ioread32(gdev->base + ARB_ERR_CAP_ADDR) & 0xffffffff;
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arb_addr = gisb_read(gdev, ARB_ERR_CAP_ADDR) & 0xffffffff;
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#if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
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arb_addr |= (u64)ioread32(gdev->base + ARB_ERR_CAP_HI_ADDR) << 32;
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arb_addr |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
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#endif
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master = ioread32(gdev->base + ARB_ERR_CAP_MASTER);
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master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
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m_name = brcmstb_gisb_master_to_str(gdev, master);
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if (!m_name) {
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@ -136,11 +202,12 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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m_name);
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/* clear the GISB error */
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iowrite32(ARB_ERR_CAP_CLEAR, gdev->base + ARB_ERR_CAP_CLR);
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gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
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return 0;
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}
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#ifdef CONFIG_ARM
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static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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@ -165,6 +232,7 @@ void __init brcmstb_hook_fault_code(void)
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hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
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"imprecise external abort");
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}
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#endif
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static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
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{
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@ -192,10 +260,20 @@ static struct attribute_group gisb_arb_sysfs_attr_group = {
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.attrs = gisb_arb_sysfs_attrs,
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};
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static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
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{ .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 },
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{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
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{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
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{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
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{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
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{ },
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};
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static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
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{
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struct device_node *dn = pdev->dev.of_node;
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struct brcmstb_gisb_arb_device *gdev;
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const struct of_device_id *of_id;
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struct resource *r;
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int err, timeout_irq, tea_irq;
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unsigned int num_masters, j = 0;
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@ -216,6 +294,13 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
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if (IS_ERR(gdev->base))
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return PTR_ERR(gdev->base);
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of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
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if (!of_id) {
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pr_err("failed to look up compatible string\n");
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return -EINVAL;
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}
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gdev->gisb_offsets = of_id->data;
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err = devm_request_irq(&pdev->dev, timeout_irq,
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brcmstb_gisb_timeout_handler, 0, pdev->name,
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gdev);
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@ -267,11 +352,6 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
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{ .compatible = "brcm,gisb-arb" },
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{ },
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};
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static struct platform_driver brcmstb_gisb_arb_driver = {
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.driver = {
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.name = "brcm-gisb-arb",
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