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ARM: dts: Add apf51 basic support

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Signed-off-by: Laurent Cans <laurent.cans@gmail.com>
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Laurent Cans 2013-01-20 23:55:29 +01:00 committed by Shawn Guo
parent a5120e89e7
commit 1982d5b6c1
4 changed files with 89 additions and 0 deletions
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6
Documentation/devicetree/bindings/arm/armadeus.txt Normal file
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@ -0,0 +1,6 @@
Armadeus i.MX Platforms Device Tree Bindings
-----------------------------------------------
APF51: i.MX51 based module.
Required root node properties:
- compatible = "armadeus,imx51-apf51", "fsl,imx51";

1
arch/arm/boot/dts/Makefile
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@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-apf27.dtb \
imx27-pdk.dtb \
imx31-bug.dtb \
imx51-apf51.dtb \
imx51-babbage.dtb \
imx53-ard.dtb \
imx53-evk.dtb \

52
arch/arm/boot/dts/imx51-apf51.dts Normal file
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@ -0,0 +1,52 @@
/*
* Copyright 2012 Armadeus Systems - <support@armadeus.com>
* Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
*
* Based on mx51-babbage.dts
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx51.dtsi"
/ {
model = "Armadeus Systems APF51 module";
compatible = "armadeus,imx51-apf51", "fsl,imx51";
memory {
reg = <0x90000000 0x20000000>;
};
clocks {
ckih1 {
clock-frequency = <0>;
};
osc {
clock-frequency = <33554432>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_2>;
phy-mode = "mii";
phy-reset-gpios = <&gpio3 0 0>;
phy-reset-duration = <1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;
status = "okay";
};

30
arch/arm/boot/dts/imx51.dtsi
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@ -281,6 +281,29 @@ pinctrl_fec_1: fecgrp-1 {
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
>;
};
};
ecspi1 {
@ -417,6 +440,13 @@ pinctrl_uart3_1: uart3grp-1 {
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
>;
};
pinctrl_uart3_2: uart3grp-2 {
fsl,pins = <
434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
>;
};
};
kpp {