forked from luck/tmp_suning_uos_patched
mfd: Remove custom wm8350 cache implementation
Since none of the users now reference the cache directly we can happily remove the custom cache code and rely on the regmap cache. For simplicity we don't bother with the register defaults tables but instead read the defaults from the device - regmap is capable of doing this, unlike our old cache infrastructure. This saves a lot of code and allows us to cache the device revision information too. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Mark Brown
Samuel Ortiz
parent
7fdb5d3261
commit
19d57ed5a3
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@ -60,181 +60,32 @@
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/*
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* WM8350 Device IO
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*/
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static DEFINE_MUTEX(io_mutex);
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static DEFINE_MUTEX(reg_lock_mutex);
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/* Perform a physical read from the device.
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*/
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static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
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u16 *dest)
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{
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int i, ret;
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int bytes = num_regs * 2;
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dev_dbg(wm8350->dev, "volatile read\n");
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ret = regmap_raw_read(wm8350->regmap, reg, dest, bytes);
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for (i = reg; i < reg + num_regs; i++) {
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/* Cache is CPU endian */
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dest[i - reg] = be16_to_cpu(dest[i - reg]);
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/* Mask out non-readable bits */
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dest[i - reg] &= wm8350_reg_io_map[i].readable;
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}
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dump(num_regs, dest);
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return ret;
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}
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static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
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{
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int i;
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int end = reg + num_regs;
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int ret = 0;
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int bytes = num_regs * 2;
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if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
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dev_err(wm8350->dev, "invalid reg %x\n",
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reg + num_regs - 1);
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return -EINVAL;
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}
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dev_dbg(wm8350->dev,
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"%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
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#if WM8350_BUS_DEBUG
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/* we can _safely_ read any register, but warn if read not supported */
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for (i = reg; i < end; i++) {
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if (!wm8350_reg_io_map[i].readable)
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dev_warn(wm8350->dev,
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"reg R%d is not readable\n", i);
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}
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#endif
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/* if any volatile registers are required, then read back all */
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for (i = reg; i < end; i++)
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if (wm8350_reg_io_map[i].vol)
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return wm8350_phys_read(wm8350, reg, num_regs, dest);
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/* no volatiles, then cache is good */
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dev_dbg(wm8350->dev, "cache read\n");
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memcpy(dest, &wm8350->reg_cache[reg], bytes);
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dump(num_regs, dest);
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return ret;
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}
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static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
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{
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if (reg == WM8350_SECURITY ||
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wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
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return 0;
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if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
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reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
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(reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
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reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
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return 1;
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return 0;
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}
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static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
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{
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int i;
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int end = reg + num_regs;
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int bytes = num_regs * 2;
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if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
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dev_err(wm8350->dev, "invalid reg %x\n",
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reg + num_regs - 1);
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return -EINVAL;
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}
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/* it's generally not a good idea to write to RO or locked registers */
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for (i = reg; i < end; i++) {
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if (!wm8350_reg_io_map[i].writable) {
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dev_err(wm8350->dev,
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"attempted write to read only reg R%d\n", i);
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return -EINVAL;
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}
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if (is_reg_locked(wm8350, i)) {
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dev_err(wm8350->dev,
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"attempted write to locked reg R%d\n", i);
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return -EINVAL;
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}
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src[i - reg] &= wm8350_reg_io_map[i].writable;
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wm8350->reg_cache[i] =
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(wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
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| src[i - reg];
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src[i - reg] = cpu_to_be16(src[i - reg]);
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}
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/* Actually write it out */
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return regmap_raw_write(wm8350->regmap, reg, src, bytes);
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}
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/*
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* Safe read, modify, write methods
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*/
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int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
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{
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u16 data;
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int err;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, reg, 1, &data);
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if (err) {
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dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
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goto out;
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}
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data &= ~mask;
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err = wm8350_write(wm8350, reg, 1, &data);
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if (err)
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dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
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out:
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mutex_unlock(&io_mutex);
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return err;
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return regmap_update_bits(wm8350->regmap, reg, mask, 0);
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}
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EXPORT_SYMBOL_GPL(wm8350_clear_bits);
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int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
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{
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u16 data;
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int err;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, reg, 1, &data);
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if (err) {
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dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
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goto out;
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}
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data |= mask;
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err = wm8350_write(wm8350, reg, 1, &data);
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if (err)
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dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
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out:
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mutex_unlock(&io_mutex);
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return err;
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return regmap_update_bits(wm8350->regmap, reg, mask, mask);
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}
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EXPORT_SYMBOL_GPL(wm8350_set_bits);
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u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
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{
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u16 data;
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unsigned int data;
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int err;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, reg, 1, &data);
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err = regmap_read(wm8350->regmap, reg, &data);
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if (err)
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dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
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mutex_unlock(&io_mutex);
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return data;
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}
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EXPORT_SYMBOL_GPL(wm8350_reg_read);
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@ -242,13 +93,11 @@ EXPORT_SYMBOL_GPL(wm8350_reg_read);
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int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
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{
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int ret;
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u16 data = val;
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mutex_lock(&io_mutex);
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ret = wm8350_write(wm8350, reg, 1, &data);
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ret = regmap_write(wm8350->regmap, reg, val);
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if (ret)
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dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
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mutex_unlock(&io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(wm8350_reg_write);
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@ -258,12 +107,11 @@ int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
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{
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int err = 0;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, start_reg, regs, dest);
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err = regmap_bulk_read(wm8350->regmap, start_reg, dest, regs);
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if (err)
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dev_err(wm8350->dev, "block read starting from R%d failed\n",
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start_reg);
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mutex_unlock(&io_mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(wm8350_block_read);
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@ -273,12 +121,11 @@ int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
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{
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int ret = 0;
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mutex_lock(&io_mutex);
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ret = wm8350_write(wm8350, start_reg, regs, src);
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ret = regmap_bulk_write(wm8350->regmap, start_reg, src, regs);
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if (ret)
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dev_err(wm8350->dev, "block write starting at R%d failed\n",
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start_reg);
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mutex_unlock(&io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(wm8350_block_write);
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@ -401,146 +248,6 @@ static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data)
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return IRQ_HANDLED;
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}
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/*
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* Cache is always host endian.
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*/
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static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
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{
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int i, ret = 0;
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u16 value;
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const u16 *reg_map;
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switch (type) {
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case 0:
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switch (mode) {
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#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
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case 0:
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reg_map = wm8350_mode0_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
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case 1:
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reg_map = wm8350_mode1_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
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case 2:
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reg_map = wm8350_mode2_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
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case 3:
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reg_map = wm8350_mode3_defaults;
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break;
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#endif
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default:
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dev_err(wm8350->dev,
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"WM8350 configuration mode %d not supported\n",
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mode);
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return -EINVAL;
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}
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break;
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case 1:
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switch (mode) {
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#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
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case 0:
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reg_map = wm8351_mode0_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
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case 1:
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reg_map = wm8351_mode1_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
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case 2:
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reg_map = wm8351_mode2_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
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case 3:
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reg_map = wm8351_mode3_defaults;
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break;
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#endif
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default:
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dev_err(wm8350->dev,
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"WM8351 configuration mode %d not supported\n",
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mode);
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return -EINVAL;
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}
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break;
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case 2:
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switch (mode) {
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#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
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case 0:
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reg_map = wm8352_mode0_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
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case 1:
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reg_map = wm8352_mode1_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
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case 2:
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reg_map = wm8352_mode2_defaults;
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break;
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#endif
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#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
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case 3:
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reg_map = wm8352_mode3_defaults;
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break;
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#endif
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default:
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dev_err(wm8350->dev,
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"WM8352 configuration mode %d not supported\n",
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mode);
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return -EINVAL;
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}
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break;
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default:
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dev_err(wm8350->dev,
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"WM835x configuration mode %d not supported\n",
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mode);
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return -EINVAL;
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}
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wm8350->reg_cache =
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kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
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if (wm8350->reg_cache == NULL)
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return -ENOMEM;
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/* Read the initial cache state back from the device - this is
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* a PMIC so the device many not be in a virgin state and we
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* can't rely on the silicon values.
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*/
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ret = regmap_raw_read(wm8350->regmap, 0, wm8350->reg_cache,
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sizeof(u16) * (WM8350_MAX_REGISTER + 1));
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if (ret < 0) {
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dev_err(wm8350->dev,
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"failed to read initial cache values\n");
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goto out;
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}
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/* Mask out uncacheable/unreadable bits and the audio. */
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for (i = 0; i < WM8350_MAX_REGISTER; i++) {
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if (wm8350_reg_io_map[i].readable &&
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(i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
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value = be16_to_cpu(wm8350->reg_cache[i]);
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value &= wm8350_reg_io_map[i].readable;
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wm8350->reg_cache[i] = value;
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} else
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wm8350->reg_cache[i] = reg_map[i];
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}
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out:
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kfree(wm8350->reg_cache);
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return ret;
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}
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/*
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* Register a client device. This is non-fatal since there is no need to
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* fail the entire device init due to a single platform device failing.
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@ -688,18 +395,12 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
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goto err;
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}
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ret = wm8350_create_cache(wm8350, mask_rev, mode);
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if (ret < 0) {
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dev_err(wm8350->dev, "Failed to create register cache\n");
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return ret;
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}
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mutex_init(&wm8350->auxadc_mutex);
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init_completion(&wm8350->auxadc_done);
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ret = wm8350_irq_init(wm8350, irq, pdata);
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if (ret < 0)
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goto err_free;
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goto err;
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if (wm8350->irq_base) {
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ret = request_threaded_irq(wm8350->irq_base +
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@ -737,8 +438,6 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
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err_irq:
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wm8350_irq_exit(wm8350);
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err_free:
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kfree(wm8350->reg_cache);
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err:
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return ret;
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}
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@ -765,8 +464,6 @@ void wm8350_device_exit(struct wm8350 *wm8350)
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free_irq(wm8350->irq_base + WM8350_IRQ_AUXADC_DATARDY, wm8350);
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wm8350_irq_exit(wm8350);
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kfree(wm8350->reg_cache);
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}
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EXPORT_SYMBOL_GPL(wm8350_device_exit);
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File diff suppressed because it is too large
Load Diff
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@ -587,24 +587,6 @@
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#define WM8350_NUM_IRQ_REGS 7
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extern const struct regmap_config wm8350_regmap;
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struct wm8350_reg_access {
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u16 readable; /* Mask of readable bits */
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u16 writable; /* Mask of writable bits */
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u16 vol; /* Mask of volatile bits */
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};
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extern const struct wm8350_reg_access wm8350_reg_io_map[];
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extern const u16 wm8350_mode0_defaults[];
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extern const u16 wm8350_mode1_defaults[];
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extern const u16 wm8350_mode2_defaults[];
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extern const u16 wm8350_mode3_defaults[];
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extern const u16 wm8351_mode0_defaults[];
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extern const u16 wm8351_mode1_defaults[];
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extern const u16 wm8351_mode2_defaults[];
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extern const u16 wm8351_mode3_defaults[];
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extern const u16 wm8352_mode0_defaults[];
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extern const u16 wm8352_mode1_defaults[];
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extern const u16 wm8352_mode2_defaults[];
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extern const u16 wm8352_mode3_defaults[];
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struct wm8350;
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@ -618,7 +600,6 @@ struct wm8350 {
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/* device IO */
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struct regmap *regmap;
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u16 *reg_cache;
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bool unlocked;
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struct mutex auxadc_mutex;
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