forked from luck/tmp_suning_uos_patched
ARM: OMAP2+: gpmc: remove cs# in sync clk div calc
Divider value for a certain sync clk is determined solely based on gpmc fclk. CS# does not have any role here, thus remove presence of CS# in clock divider calculation API. Signed-off-by: Afzal Mohammed <afzal@ti.com> Reviewed-by: Jon Hunter <jon-hunter@ti.com>
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@ -231,7 +231,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
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break;
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}
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div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
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div = gpmc_calc_divider(min_gpmc_clk_period);
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gpmc_clk_ns = gpmc_ticks_to_ns(div);
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if (gpmc_clk_ns < 15) /* >66Mhz */
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onenand_flags |= ONENAND_FLAG_HF;
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@ -288,7 +288,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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return -1
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#endif
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int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
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int gpmc_calc_divider(unsigned int sync_clk)
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{
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int div;
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u32 l;
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@ -308,7 +308,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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int div;
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u32 l;
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div = gpmc_cs_calc_divider(cs, t->sync_clk);
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div = gpmc_calc_divider(t->sync_clk);
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if (div < 0)
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return div;
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@ -160,7 +160,7 @@ extern unsigned long gpmc_get_fclk_period(void);
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extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
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extern u32 gpmc_cs_read_reg(int cs, int idx);
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extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
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extern int gpmc_calc_divider(unsigned int sync_clk);
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extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
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extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
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extern void gpmc_cs_free(int cs);
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