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powerpc/64: flush_inval_dcache_range() becomes flush_dcache_range()

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On most arches having function flush_dcache_range(), including PPC32,
this function does a writeback and invalidation of the cache bloc.

On PPC64, flush_dcache_range() only does a writeback while
flush_inval_dcache_range() does the invalidation in addition.

In addition it looks like within arch/powerpc/, there are no PPC64
platforms using flush_dcache_range()

This patch drops the existing 64 bits version of flush_dcache_range()
and renames flush_inval_dcache_range() into flush_dcache_range().

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Leroy 2019-05-14 09:05:13 +00:00 committed by Michael Ellerman
parent 6c5875843b
commit 1cfb725fb1
6 changed files with 11 additions and 35 deletions
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1
arch/powerpc/include/asm/cacheflush.h
View File

@ -112,7 +112,6 @@ static inline void invalidate_dcache_range(unsigned long start,
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC64
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
#endif
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \

27
arch/powerpc/kernel/misc_64.S
View File

@ -121,31 +121,8 @@ EXPORT_SYMBOL(flush_icache_range)
*
* flush all bytes from start to stop-1 inclusive
*/
_GLOBAL_TOC(flush_dcache_range)
/*
* Flush the data cache to memory
*
* Different systems have different cache line sizes
*/
ld r10,PPC64_CACHES@toc(r2)
lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */
addi r5,r7,-1
andc r6,r3,r5 /* round low to line bdy */
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */
srw. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
0: dcbst 0,r6
add r6,r6,r7
bdnz 0b
sync
blr
EXPORT_SYMBOL(flush_dcache_range)
_GLOBAL(flush_inval_dcache_range)
ld r10,PPC64_CACHES@toc(r2)
lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */
addi r5,r7,-1
@ -164,7 +141,7 @@ _GLOBAL(flush_inval_dcache_range)
sync
isync
blr
EXPORT_SYMBOL(flush_dcache_range)
/*
* Flush a particular page from the data cache to RAM.

8
arch/powerpc/lib/pmem.c
View File

@ -23,14 +23,14 @@
void arch_wb_cache_pmem(void *addr, size_t size)
{
unsigned long start = (unsigned long) addr;
flush_inval_dcache_range(start, start + size);
flush_dcache_range(start, start + size);
}
EXPORT_SYMBOL(arch_wb_cache_pmem);
void arch_invalidate_pmem(void *addr, size_t size)
{
unsigned long start = (unsigned long) addr;
flush_inval_dcache_range(start, start + size);
flush_dcache_range(start, start + size);
}
EXPORT_SYMBOL(arch_invalidate_pmem);
@ -43,7 +43,7 @@ long __copy_from_user_flushcache(void *dest, const void __user *src,
unsigned long copied, start = (unsigned long) dest;
copied = __copy_from_user(dest, src, size);
flush_inval_dcache_range(start, start + size);
flush_dcache_range(start, start + size);
return copied;
}
@ -53,7 +53,7 @@ void *memcpy_flushcache(void *dest, const void *src, size_t size)
unsigned long start = (unsigned long) dest;
memcpy(dest, src, size);
flush_inval_dcache_range(start, start + size);
flush_dcache_range(start, start + size);
return dest;
}

4
arch/powerpc/mm/mem.c
View File

@ -125,7 +125,7 @@ int __ref arch_add_memory(int nid, u64 start, u64 size,
start, start + size, rc);
return -EFAULT;
}
flush_inval_dcache_range(start, start + size);
flush_dcache_range(start, start + size);
return __add_pages(nid, start_pfn, nr_pages, restrictions);
}
@ -151,7 +151,7 @@ void __ref arch_remove_memory(int nid, u64 start, u64 size,
/* Remove htab bolted mappings for this section of memory */
start = (unsigned long)__va(start);
flush_inval_dcache_range(start, start + size);
flush_dcache_range(start, start + size);
ret = remove_section_mapping(start, start + size);
WARN_ON_ONCE(ret);

2
arch/powerpc/sysdev/dart_iommu.c
View File

@ -158,7 +158,7 @@ static void dart_cache_sync(unsigned int *base, unsigned int count)
unsigned int tmp;
/* Perform a standard cache flush */
flush_inval_dcache_range(start, end);
flush_dcache_range(start, end);
/*
* Perform the sequence described in the CPC925 manual to

4
drivers/macintosh/smu.c
View File

@ -133,7 +133,7 @@ static void smu_start_cmd(void)
/* Flush command and data to RAM */
faddr = (unsigned long)smu->cmd_buf;
fend = faddr + smu->cmd_buf->length + 2;
flush_inval_dcache_range(faddr, fend);
flush_dcache_range(faddr, fend);
/* We also disable NAP mode for the duration of the command
@ -195,7 +195,7 @@ static irqreturn_t smu_db_intr(int irq, void *arg)
* reply length (it's only 2 cache lines anyway)
*/
faddr = (unsigned long)smu->cmd_buf;
flush_inval_dcache_range(faddr, faddr + 256);
flush_dcache_range(faddr, faddr + 256);
/* Now check ack */
ack = (~cmd->cmd) & 0xff;