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drm/i915/gvt: fix an error for one register

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register 0x20e0 should be mode register

v2: rebased to latest code base

Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Zhao Yan 2017-02-28 15:41:03 +08:00 committed by Zhenyu Wang
parent 9112caafdf
commit 1f58af304c
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/i915/gvt/handlers.c
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@ -2749,7 +2749,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);
MMIO_D(0xd08, D_SKL);
MMIO_D(0x20e0, D_SKL);
MMIO_DFH(0x20e0, D_SKL, F_MODE_MASK, NULL, NULL);
MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
/* TRTT */