From 2170480487e3dee8a74204ce346b1b1096a13fd0 Mon Sep 17 00:00:00 2001 From: Joe Schultz Date: Mon, 7 Apr 2014 11:58:18 -0500 Subject: [PATCH] mtd: fsl_ifc_nand: Workaround bogus WP on 16-bit NAND A workaround was already in place that set the WP bit in the IFC_CSPR0 register after a STATUS command, however it used an 8-bit write method. As a result, the WP bit was never set on 16-bit devices, and these devices would eventually be incorrectly marked as write-protected. This patch checks the chip options for a 16-bit device and uses the appropriate write method to set the WP bit after a STATUS command. Signed-off-by: Joe Schultz Signed-off-by: Aaron Sierra Signed-off-by: Brian Norris --- drivers/mtd/nand/fsl_ifc_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 8ed0ee1cfee1..2338124dd05f 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -591,7 +591,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, * The chip always seems to report that it is * write-protected, even when it is not. */ - setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); + if (chip->options & NAND_BUSWIDTH_16) + setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP); + else + setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); return; case NAND_CMD_RESET: