forked from luck/tmp_suning_uos_patched
[POWERPC] cell: update Cell BE register definitions
There are a few definitions that are required by subsequent patches, so add them here. The original patch is from David Erb, but is significantly cleaned up by Kevon Corry. Cc: Kevin Corry <kevcorry@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Erb
Paul Mackerras
parent
099814bb1f
commit
22b8c9f5ba
@ -8,6 +8,7 @@
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#include <linux/percpu.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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@ -16,8 +17,6 @@
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#include "cbe_regs.h"
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#define MAX_CBE 2
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/*
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* Current implementation uses "cpu" nodes. We build our own mapping
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* array of cpu numbers to cpu nodes locally for now to allow interrupt
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@ -30,6 +29,7 @@ static struct cbe_regs_map
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struct device_node *cpu_node;
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struct cbe_pmd_regs __iomem *pmd_regs;
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struct cbe_iic_regs __iomem *iic_regs;
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struct cbe_mic_tm_regs __iomem *mic_tm_regs;
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} cbe_regs_maps[MAX_CBE];
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static int cbe_regs_map_count;
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@ -42,6 +42,19 @@ static struct cbe_thread_map
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static struct cbe_regs_map *cbe_find_map(struct device_node *np)
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{
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int i;
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struct device_node *tmp_np;
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if (strcasecmp(np->type, "spe") == 0) {
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if (np->data == NULL) {
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/* walk up path until cpu node was found */
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tmp_np = np->parent;
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while (tmp_np != NULL && strcasecmp(tmp_np->type, "cpu") != 0)
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tmp_np = tmp_np->parent;
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np->data = cbe_find_map(tmp_np);
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}
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return np->data;
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}
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for (i = 0; i < cbe_regs_map_count; i++)
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if (cbe_regs_maps[i].cpu_node == np)
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@ -56,6 +69,7 @@ struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np)
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return NULL;
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return map->pmd_regs;
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}
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EXPORT_SYMBOL_GPL(cbe_get_pmd_regs);
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struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu)
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{
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@ -64,7 +78,7 @@ struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu)
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return NULL;
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return map->pmd_regs;
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}
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EXPORT_SYMBOL_GPL(cbe_get_cpu_pmd_regs);
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struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np)
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{
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@ -73,6 +87,7 @@ struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np)
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return NULL;
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return map->iic_regs;
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}
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struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu)
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{
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struct cbe_regs_map *map = cbe_thread_map[cpu].regs;
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@ -81,6 +96,24 @@ struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu)
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return map->iic_regs;
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}
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struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np)
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{
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struct cbe_regs_map *map = cbe_find_map(np);
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if (map == NULL)
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return NULL;
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return map->mic_tm_regs;
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}
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struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu)
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{
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struct cbe_regs_map *map = cbe_thread_map[cpu].regs;
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if (map == NULL)
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return NULL;
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return map->mic_tm_regs;
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}
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EXPORT_SYMBOL_GPL(cbe_get_cpu_mic_tm_regs);
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void __init cbe_regs_init(void)
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{
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int i;
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@ -119,6 +152,11 @@ void __init cbe_regs_init(void)
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prop = get_property(cpu, "iic", NULL);
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if (prop != NULL)
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map->iic_regs = ioremap(prop->address, prop->len);
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prop = (struct address_prop *)get_property(cpu, "mic-tm",
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NULL);
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if (prop != NULL)
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map->mic_tm_regs = ioremap(prop->address, prop->len);
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}
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}
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@ -4,6 +4,11 @@
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* This file is intended to hold the various register definitions for CBE
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* on-chip system devices (memory controller, IO controller, etc...)
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*
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* (C) Copyright IBM Corporation 2001,2006
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*
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* Authors: Maximino Aguilar (maguilar@us.ibm.com)
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* David J. Erb (djerb@us.ibm.com)
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*
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* (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*/
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@ -22,6 +27,7 @@
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#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
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#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
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#define MAX_CBE 2
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/*
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*
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@ -29,45 +35,86 @@
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*
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*/
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union spe_reg {
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u64 val;
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u8 spe[8];
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};
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union ppe_spe_reg {
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u64 val;
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struct {
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u32 ppe;
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u32 spe;
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};
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};
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struct cbe_pmd_regs {
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u8 pad_0x0000_0x0800[0x0800 - 0x0000]; /* 0x0000 */
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/* Debug Bus Control */
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u64 pad_0x0000; /* 0x0000 */
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u64 group_control; /* 0x0008 */
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u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
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u64 debug_bus_control; /* 0x00a8 */
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u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
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u64 trace_aux_data; /* 0x0100 */
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u64 trace_buffer_0_63; /* 0x0108 */
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u64 trace_buffer_64_127; /* 0x0110 */
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u64 trace_address; /* 0x0118 */
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u64 ext_tr_timer; /* 0x0120 */
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u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
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/* Performance Monitor */
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u64 pm_status; /* 0x0400 */
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u64 pm_control; /* 0x0408 */
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u64 pm_interval; /* 0x0410 */
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u64 pm_ctr[4]; /* 0x0418 */
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u64 pm_start_stop; /* 0x0438 */
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u64 pm07_control[8]; /* 0x0440 */
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u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
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/* Thermal Sensor Registers */
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u64 ts_ctsr1; /* 0x0800 */
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u64 ts_ctsr2; /* 0x0808 */
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u64 ts_mtsr1; /* 0x0810 */
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u64 ts_mtsr2; /* 0x0818 */
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u64 ts_itr1; /* 0x0820 */
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u64 ts_itr2; /* 0x0828 */
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u64 ts_gitr; /* 0x0830 */
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u64 ts_isr; /* 0x0838 */
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u64 ts_imr; /* 0x0840 */
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u64 tm_cr1; /* 0x0848 */
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u64 tm_cr2; /* 0x0850 */
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u64 tm_simr; /* 0x0858 */
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u64 tm_tpr; /* 0x0860 */
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u64 tm_str1; /* 0x0868 */
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u64 tm_str2; /* 0x0870 */
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u64 tm_tsr; /* 0x0878 */
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union spe_reg ts_ctsr1; /* 0x0800 */
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u64 ts_ctsr2; /* 0x0808 */
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union spe_reg ts_mtsr1; /* 0x0810 */
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u64 ts_mtsr2; /* 0x0818 */
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union spe_reg ts_itr1; /* 0x0820 */
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u64 ts_itr2; /* 0x0828 */
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u64 ts_gitr; /* 0x0830 */
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u64 ts_isr; /* 0x0838 */
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u64 ts_imr; /* 0x0840 */
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union spe_reg tm_cr1; /* 0x0848 */
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u64 tm_cr2; /* 0x0850 */
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u64 tm_simr; /* 0x0858 */
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union ppe_spe_reg tm_tpr; /* 0x0860 */
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union spe_reg tm_str1; /* 0x0868 */
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u64 tm_str2; /* 0x0870 */
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union ppe_spe_reg tm_tsr; /* 0x0878 */
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/* Power Management */
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u64 pm_control; /* 0x0880 */
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#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
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u64 pm_status; /* 0x0888 */
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u64 pmcr; /* 0x0880 */
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#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
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u64 pmsr; /* 0x0888 */
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/* Time Base Register */
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u64 tbr; /* 0x0890 */
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u64 tbr; /* 0x0890 */
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u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
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u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
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/* Fault Isolation Registers */
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u64 checkstop_fir; /* 0x0c00 */
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u64 recoverable_fir;
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u64 spec_att_mchk_fir;
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u64 fir_mode_reg;
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u64 fir_enable_mask;
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u64 checkstop_fir; /* 0x0c00 */
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u64 recoverable_fir; /* 0x0c08 */
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u64 spec_att_mchk_fir; /* 0x0c10 */
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u64 fir_mode_reg; /* 0x0c18 */
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u64 fir_enable_mask; /* 0x0c20 */
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u8 pad_0x0c28_0x1000 [0x1000 - 0x0c28]; /* 0x0c28 */
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u8 pad_0x0c28_0x1000 [0x1000 - 0x0c28]; /* 0x0c28 */
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};
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extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
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@ -102,18 +149,20 @@ struct cbe_iic_regs {
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/* IIC interrupt registers */
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struct cbe_iic_thread_regs thread[2]; /* 0x0400 */
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u64 iic_ir; /* 0x0440 */
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u64 iic_is; /* 0x0448 */
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u64 iic_ir; /* 0x0440 */
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u64 iic_is; /* 0x0448 */
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#define CBE_IIC_IS_PMI 0x2
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u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
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/* IOC FIR */
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u64 ioc_fir_reset; /* 0x0500 */
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u64 ioc_fir_set;
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u64 ioc_checkstop_enable;
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u64 ioc_fir_error_mask;
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u64 ioc_syserr_enable;
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u64 ioc_fir;
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u64 ioc_fir_set; /* 0x0508 */
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u64 ioc_checkstop_enable; /* 0x0510 */
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u64 ioc_fir_error_mask; /* 0x0518 */
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u64 ioc_syserr_enable; /* 0x0520 */
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u64 ioc_fir; /* 0x0528 */
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u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
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};
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@ -122,6 +171,48 @@ extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
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extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
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struct cbe_mic_tm_regs {
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u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
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u64 mic_ctl_cnfg2; /* 0x0040 */
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#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL
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#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL
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#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL
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#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL
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u64 pad_0x0048; /* 0x0048 */
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u64 mic_aux_trc_base; /* 0x0050 */
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u64 mic_aux_trc_max_addr; /* 0x0058 */
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u64 mic_aux_trc_cur_addr; /* 0x0060 */
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u64 mic_aux_trc_grf_addr; /* 0x0068 */
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u64 mic_aux_trc_grf_data; /* 0x0070 */
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u64 pad_0x0078; /* 0x0078 */
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u64 mic_ctl_cnfg_0; /* 0x0080 */
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#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL
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u64 pad_0x0088; /* 0x0088 */
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u64 slow_fast_timer_0; /* 0x0090 */
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u64 slow_next_timer_0; /* 0x0098 */
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u8 pad_0x00a0_0x01c0[0x01c0 - 0x0a0]; /* 0x00a0 */
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u64 mic_ctl_cnfg_1; /* 0x01c0 */
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#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL
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u64 pad_0x01c8; /* 0x01c8 */
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u64 slow_fast_timer_1; /* 0x01d0 */
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u64 slow_next_timer_1; /* 0x01d8 */
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u8 pad_0x01e0_0x1000[0x1000 - 0x01e0]; /* 0x01e0 */
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};
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extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
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extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
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/* Init this module early */
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extern void cbe_regs_init(void);
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@ -54,9 +54,9 @@ static void __init cbe_enable_pause_zero(void)
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pr_debug("Power Management: CPU %d\n", smp_processor_id());
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/* Enable Pause(0) control bit */
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temp_register = in_be64(&pregs->pm_control);
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temp_register = in_be64(&pregs->pmcr);
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out_be64(&pregs->pm_control,
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out_be64(&pregs->pmcr,
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temp_register | CBE_PMD_PAUSE_ZERO_CONTROL);
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/* Enable DEC and EE interrupt request */
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@ -87,7 +87,7 @@ static void cbe_idle(void)
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unsigned long ctrl;
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/* Why do we do that on every idle ? Couldn't that be done once for
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* all or do we lose the state some way ? Also, the pm_control
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* all or do we lose the state some way ? Also, the pmcr
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* register setting, that can't be set once at boot ? We really want
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* to move that away in order to implement a simple powersave
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*/
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