forked from luck/tmp_suning_uos_patched
OMAP2+: clock: remove the DPLL rate tolerance code
Remove the DPLL rate tolerance code that is called during rate rounding. As far as I know, this code is never used, since it's been more important for callers of the DPLL round_rate()/set_rate() functions to obtain an exact rate than it is to save a relatively small amount of power. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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e07f469d28
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241d3a8dca
@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
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if (!dd)
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return;
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/* Return bypass rate if DPLL is bypassed */
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v = __raw_readl(dd->control_reg);
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v &= dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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/* Reparent in case the dpll is in bypass */
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/* Reparent the struct clk in case the dpll is in bypass */
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if (cpu_is_omap24xx()) {
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if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
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v == OMAP2XXX_EN_DPLL_FRBYPASS)
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@ -259,51 +258,23 @@ u32 omap2_get_dpll_rate(struct clk *clk)
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/* DPLL rate rounding code */
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/**
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* omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
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* @clk: struct clk * of the DPLL
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* @tolerance: maximum rate error tolerance
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*
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* Set the maximum DPLL rate error tolerance for the rate rounding
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* algorithm. The rate tolerance is an attempt to balance DPLL power
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* saving (the least divider value "n") vs. rate fidelity (the least
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* difference between the desired DPLL target rate and the rounded
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* rate out of the algorithm). So, increasing the tolerance is likely
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* to decrease DPLL power consumption and increase DPLL rate error.
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* Returns -EINVAL if provided a null clock ptr or a clk that is not a
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* DPLL; or 0 upon success.
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*/
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int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
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{
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if (!clk || !clk->dpll_data)
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return -EINVAL;
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clk->dpll_data->rate_tolerance = tolerance;
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return 0;
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}
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/**
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* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
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* @clk: struct clk * for a DPLL
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* @target_rate: desired DPLL clock rate
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*
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* Given a DPLL, a desired target rate, and a rate tolerance, round
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* the target rate to a possible, programmable rate for this DPLL.
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* Rate tolerance is assumed to be set by the caller before this
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* function is called. Attempts to select the minimum possible n
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* within the tolerance to reduce power consumption. Stores the
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* computed (m, n) in the DPLL's dpll_data structure so set_rate()
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* will not need to call this (expensive) function again. Returns ~0
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* if the target rate cannot be rounded, either because the rate is
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* too low or because the rate tolerance is set too tightly; or the
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* rounded rate upon success.
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* Given a DPLL and a desired target rate, round the target rate to a
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* possible, programmable rate for this DPLL. Attempts to select the
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* minimum possible n. Stores the computed (m, n) in the DPLL's
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* dpll_data structure so set_rate() will not need to call this
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* (expensive) function again. Returns ~0 if the target rate cannot
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* be rounded, or the rounded rate upon success.
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*/
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
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{
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int m, n, r, e, scaled_max_m;
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unsigned long scaled_rt_rp, new_rate;
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int min_e = -1, min_e_m = -1, min_e_n = -1;
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int m, n, r, scaled_max_m;
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unsigned long scaled_rt_rp;
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unsigned long new_rate = 0;
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struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
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dd = clk->dpll_data;
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pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
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"%ld\n", clk->name, target_rate);
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pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
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clk->name, target_rate);
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scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
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scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
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@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
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if (r == DPLL_MULT_UNDERFLOW)
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continue;
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e = target_rate - new_rate;
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pr_debug("clock: n = %d: m = %d: rate error is %d "
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"(new_rate = %ld)\n", n, m, e, new_rate);
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pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
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clk->name, m, n, new_rate);
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if (min_e == -1 ||
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min_e >= (int)(abs(e) - dd->rate_tolerance)) {
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min_e = e;
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min_e_m = m;
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min_e_n = n;
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pr_debug("clock: found new least error %d\n", min_e);
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/* We found good settings -- bail out now */
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if (min_e <= dd->rate_tolerance)
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break;
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if (target_rate == new_rate) {
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dd->last_rounded_m = m;
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dd->last_rounded_n = n;
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dd->last_rounded_rate = target_rate;
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break;
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}
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}
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if (min_e < 0) {
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pr_debug("clock: error: target rate or tolerance too low\n");
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if (target_rate != new_rate) {
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pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
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target_rate);
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return ~0;
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}
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dd->last_rounded_m = min_e_m;
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dd->last_rounded_n = min_e_n;
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dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
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min_e_m, min_e_n);
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pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
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min_e, min_e_m, min_e_n);
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pr_debug("clock: final rate: %ld (target rate: %ld)\n",
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dd->last_rounded_rate, target_rate);
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return dd->last_rounded_rate;
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return target_rate;
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}
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@ -18,9 +18,6 @@
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#include <plat/clock.h>
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/* The maximum error between a target DPLL rate and the rounded rate in Hz */
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#define DEFAULT_DPLL_RATE_TOLERANCE 50000
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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#define CORE_CLK_SRC_DPLL 0x1
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@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk);
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
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int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap3_dpll_recalc(struct clk *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk *clk);
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@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = {
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.max_multiplier = 1023,
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.min_divider = 1,
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.max_divider = 16,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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/*
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@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = {
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.max_multiplier = 1023,
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.min_divider = 1,
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.max_divider = 16,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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/*
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@ -291,7 +291,6 @@ static struct dpll_data dpll1_dd = {
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.max_multiplier = OMAP3_MAX_DPLL_MULT,
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.min_divider = 1,
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.max_divider = OMAP3_MAX_DPLL_DIV,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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static struct clk dpll1_ck = {
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@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
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.max_multiplier = OMAP3_MAX_DPLL_MULT,
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.min_divider = 1,
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.max_divider = OMAP3_MAX_DPLL_DIV,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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static struct clk dpll2_ck = {
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@ -424,7 +422,6 @@ static struct dpll_data dpll3_dd = {
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.max_multiplier = OMAP3_MAX_DPLL_MULT,
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.min_divider = 1,
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.max_divider = OMAP3_MAX_DPLL_DIV,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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static struct clk dpll3_ck = {
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@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
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.max_multiplier = OMAP3_MAX_DPLL_MULT,
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.min_divider = 1,
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.max_divider = OMAP3_MAX_DPLL_DIV,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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static struct dpll_data dpll4_dd_3630 __initdata = {
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@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
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.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
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.min_divider = 1,
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.max_divider = OMAP3_MAX_DPLL_DIV,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
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.flags = DPLL_J_TYPE
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};
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@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = {
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.max_multiplier = OMAP3_MAX_DPLL_MULT,
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.min_divider = 1,
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.max_divider = OMAP3_MAX_DPLL_DIV,
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.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
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};
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static struct clk dpll5_ck = {
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@ -109,7 +109,6 @@ struct clksel {
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* @clk_ref: struct clk pointer to the clock's reference clock input
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* @control_reg: register containing the DPLL mode bitfield
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg
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* @rate_tolerance: maximum variance allowed from target rate (in Hz)
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
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* @max_multiplier: maximum valid non-bypass multiplier value (actual)
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@ -135,12 +134,9 @@ struct clksel {
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically
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* correct to only have one @clk_bypass pointer.
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*
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* XXX @rate_tolerance should probably be deprecated - currently there
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* don't seem to be any usecases for DPLL rounding that is not exact.
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*
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
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* @last_rounded_n) should be separated from the runtime-fixed fields
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* and placed into a differenct structure, so that the runtime-fixed data
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* and placed into a different structure, so that the runtime-fixed data
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* can be placed into read-only space.
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*/
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struct dpll_data {
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@ -151,7 +147,6 @@ struct dpll_data {
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struct clk *clk_ref;
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void __iomem *control_reg;
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u32 enable_mask;
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unsigned int rate_tolerance;
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unsigned long last_rounded_rate;
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u16 last_rounded_m;
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u16 max_multiplier;
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