forked from luck/tmp_suning_uos_patched
sh: Disable initial cache flush on SH-5.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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c881cbc033
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27a511c6f3
@ -63,24 +63,11 @@ static void __init speculative_execution_init(void)
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/*
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* Generic first-level cache init
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*/
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#ifdef CONFIG_SUPERH32
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static void __init cache_init(void)
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{
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unsigned long ccr, flags;
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/* First setup the rest of the I-cache info */
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current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
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current_cpu_data.icache.linesz;
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current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
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current_cpu_data.icache.linesz;
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/* And the D-cache too */
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current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
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current_cpu_data.dcache.linesz;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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jump_to_P2();
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ccr = ctrl_inl(CCR);
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@ -160,6 +147,9 @@ static void __init cache_init(void)
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ctrl_outl(flags, CCR);
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back_to_P1();
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}
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#else
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#define cache_init() do { } while (0)
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#endif
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#ifdef CONFIG_SH_DSP
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static void __init release_dsp(void)
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@ -230,6 +220,20 @@ asmlinkage void __cpuinit sh_cpu_init(void)
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if (current_cpu_data.type == CPU_SH_NONE)
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panic("Unknown CPU");
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/* First setup the rest of the I-cache info */
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current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
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current_cpu_data.icache.linesz;
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current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
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current_cpu_data.icache.linesz;
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/* And the D-cache too */
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current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
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current_cpu_data.dcache.linesz;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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/* Init the cache */
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cache_init();
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